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Date:   Wed,  6 Jul 2022 22:02:04 +0800
From:   Yixun Lan <>
        Björn Töpel <>,
Cc:     Palmer Dabbelt <>,
        Alexei Starovoitov <>,
        Daniel Borkmann <>,
        Andrii Nakryiko <>,
        Martin KaFai Lau <>,
        Song Liu <>, Yonghong Song <>,
        John Fastabend <>,
        KP Singh <>,
        Paul Walmsley <>,
        Albert Ou <>,
        Hengqi Chen <>,,, Yixun Lan <>
Subject: [PATCH] riscv, libbpf: use a0 for RC register

According to the RISC-V calling convention register usage here[1],
a0 is used as return value register, so rename it to make it consistent
with the spec.

[1] section 18.2, table 18.2

Fixes: 589fed479ba1 ("riscv, libbpf: Add RISC-V (RV64) support to bpf_tracing.h")
Signed-off-by: Yixun Lan <>


I'm adding a Fixes tag here, although the original version may just work fine,
and shouldn't be considered as a real error. But, the benefit is that we could
make it consistent with RISC-V spec, and all other tools will follow the same usage.

thanks, and let's me if there is any issue that I may not noticed..
 tools/lib/bpf/bpf_tracing.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/lib/bpf/bpf_tracing.h b/tools/lib/bpf/bpf_tracing.h
index 01ce121c302df..11f9096407fc4 100644
--- a/tools/lib/bpf/bpf_tracing.h
+++ b/tools/lib/bpf/bpf_tracing.h
@@ -233,7 +233,7 @@ struct pt_regs___arm64 {
 #define __PT_PARM5_REG a4
 #define __PT_RET_REG ra
 #define __PT_FP_REG s0
-#define __PT_RC_REG a5
+#define __PT_RC_REG a0
 #define __PT_SP_REG sp
 #define __PT_IP_REG pc
 /* riscv does not select ARCH_HAS_SYSCALL_WRAPPER. */

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