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Message-Id: <20220706213255.1473069-6-thierry.reding@gmail.com>
Date: Wed, 6 Jul 2022 23:32:51 +0200
From: Thierry Reding <thierry.reding@...il.com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: Thierry Reding <thierry.reding@...il.com>,
Jon Hunter <jonathanh@...dia.com>,
"David S . Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Bhadram Varka <vbhadram@...dia.com>,
devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
netdev@...r.kernel.org
Subject: [PATCH v3 5/9] dt-bindings: net: Add Tegra234 MGBE
From: Bhadram Varka <vbhadram@...dia.com>
Add device-tree binding documentation for the Multi-Gigabit Ethernet
(MGBE) controller found on NVIDIA Tegra234 SoCs.
Signed-off-by: Jon Hunter <jonathanh@...dia.com>
Signed-off-by: Bhadram Varka <vbhadram@...dia.com>
Signed-off-by: Thierry Reding <treding@...dia.com>
---
Changes in v3:
- add macsec and macsec-ns interrupt names
- improve mdio bus node description
- drop power-domains description
- improve bindings title
Changes in v2:
- add supported PHY modes
- change to dual license
.../bindings/net/nvidia,tegra234-mgbe.yaml | 169 ++++++++++++++++++
1 file changed, 169 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
new file mode 100644
index 000000000000..3d242ef1ca57
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
+
+maintainers:
+ - Thierry Reding <treding@...dia.com>
+ - Jon Hunter <jonathanh@...dia.com>
+
+properties:
+
+ compatible:
+ const: nvidia,tegra234-mgbe
+
+ reg:
+ minItems: 3
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: hypervisor
+ - const: mac
+ - const: xpcs
+
+ interrupts:
+ minItems: 1
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: common
+ - const: macsec-ns
+ - const: macsec
+
+ clocks:
+ minItems: 12
+ maxItems: 12
+
+ clock-names:
+ minItems: 12
+ maxItems: 12
+ contains:
+ enum:
+ - mgbe
+ - mac
+ - mac-divider
+ - ptp-ref
+ - rx-input-m
+ - rx-input
+ - tx
+ - eee-pcs
+ - rx-pcs-input
+ - rx-pcs-m
+ - rx-pcs
+ - tx-pcs
+
+ resets:
+ minItems: 2
+ maxItems: 2
+
+ reset-names:
+ contains:
+ enum:
+ - mac
+ - pcs
+
+ interconnects:
+ items:
+ - description: memory read client
+ - description: memory write client
+
+ interconnect-names:
+ items:
+ - const: dma-mem # read
+ - const: write
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ phy-handle: true
+
+ phy-mode:
+ contains:
+ enum:
+ - usxgmii
+ - 10gbase-kr
+
+ mdio:
+ $ref: mdio.yaml#
+ unevaluatedProperties: false
+ description:
+ Optional node for embedded MDIO controller.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - phy-handle
+ - phy-mode
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra234-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/memory/tegra234-mc.h>
+ #include <dt-bindings/power/tegra234-powergate.h>
+ #include <dt-bindings/reset/tegra234-reset.h>
+
+ ethernet@...0000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06800000 0x10000>,
+ <0x06810000 0x10000>,
+ <0x068a0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX>,
+ <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE0_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
+
+ phy-handle = <&mgbe0_phy>;
+ phy-mode = "usxgmii";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mgbe0_phy: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+
+ #phy-cells = <0>;
+ };
+ };
+ };
--
2.36.1
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