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Date:   Tue, 5 Jul 2022 22:55:54 -0500
From:   Samuel Holland <>
To:     Andre Przywara <>
Cc:     Chen-Yu Tsai <>,
        Jernej Skrabec <>,
        Rob Herring <>,
        Krzysztof Kozlowski <>,
        Linus Walleij <>,,,,,
        "David S. Miller" <>,
        Eric Dumazet <>,
        Jakub Kicinski <>,
        Paolo Abeni <>,
Subject: Re: [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible

Hi Andre,

On 7/5/22 5:19 AM, Andre Przywara wrote:
> On Mon, 4 Jul 2022 18:53:14 -0500
> Samuel Holland <> wrote:
>> On 7/1/22 6:24 AM, Andre Przywara wrote:
>>> The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
>>> version.
>>> Add it to the list of compatible strings.
>>> Signed-off-by: Andre Przywara <>
>>> ---
>>>  .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml       | 1 +
>>>  1 file changed, 1 insertion(+)
>>> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
>>> index 6a4831fd3616c..87f1306831cc9 100644
>>> --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
>>> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
>>> @@ -22,6 +22,7 @@ properties:
>>>            - enum:
>>>                - allwinner,sun20i-d1-emac
>>>                - allwinner,sun50i-h6-emac
>>> +              - allwinner,sun50i-h616-emac  
>> The H616 manual has register fields for an internal PHY, like H3. Are these not
>> hooked up for either EMAC?
> Which register fields do you mean, exactly?

I mean bits 15-31 of EMAC_EPHY_CLK_REG0.

> The H616 uses the same internal PHY solution as the H6: an AC200 die
> co-packaged on the carrier (or whatever integration solution they actually
> chose). The difference to the H6 is that EMAC0 is hardwired to the external
> RGMII pins, whereas EMAC1 is hardwired to the internal AC200 RMII pins.
> From all I could see that does not impact the actual MAC IP: both are the
> same as in the H6, or A64, for that matter.

If those bits in EMAC_EPHY_CLK_REG0 have no effect, then I agree. But if
switching bit 15 to internal PHY causes Ethernet to stop working, then the mux
really does exist (even if one side is not connected to anything). In that case,
we need to make sure the mux is set to the external PHY, using the code from H3.

> There is one twist, though: the second EMAC uses a separate EMAC clock
> register in the syscon. I came up with this patch to support that:
> That extends the syscon to take an optional(!) index. So EMAC0 works
> exactly like before (both as "<&syscon>;", or "<&syscon 0>;", but for EMAC1
> we need the index: "<&syscon 4>;".
> But in my opinion this should not affect the MAC binding, at least not for
> MAC0.

It definitely affects the MAC binding, because we have to change the definition
of the syscon property. We should still get that reviewed before doing anything
that depends on it. (And I think EMAC0 support depends on it.)

> And I think we should get away without a different compatible string
> for EMAC1, since the MAC IP is technically the same, it's just the
> connection that is different.

If you claim that both EMACs are compatible with allwinner,sun50i-a64-emac, then
you are saying that any existing driver for allwinner,sun50i-a64-emac will also
work with both of the H616 EMACs. But this is not true. If I hook up both EMACs
in the DT per the binding, and use the driver in master, at best only EMAC0 will
work, and likely neither will work.

So at minimum you need a new compatible for the second EMAC, so it only binds to
drivers that know about the syscon offset specifier.

> In any case I think this does not affect the level of support we promise
> today: EMAC0 with an external PHY only.

This can work if you introduce a second compatible for EMAC1. But at that point
you don't need the syscon offset specifier; it can be part of the driver data,
like for R40. (And any future EMAC1 could likely fall back to this compatible.)


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