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Date: Mon, 11 Jul 2022 22:16:00 +0800 From: Xu Kuohai <xukuohai@...wei.com> To: Jean-Philippe Brucker <jean-philippe@...aro.org> CC: <bpf@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>, Will Deacon <will@...nel.org>, KP Singh <kpsingh@...nel.org>, Mark Rutland <mark.rutland@....com>, Catalin Marinas <catalin.marinas@....com>, Daniel Borkmann <daniel@...earbox.net>, Alexei Starovoitov <ast@...nel.org>, Andrii Nakryiko <andrii@...nel.org>, Zi Shen Lim <zlim.lnx@...il.com>, Martin KaFai Lau <kafai@...com>, Song Liu <songliubraving@...com>, Yonghong Song <yhs@...com>, John Fastabend <john.fastabend@...il.com>, "David S . Miller" <davem@...emloft.net>, Hideaki YOSHIFUJI <yoshfuji@...ux-ipv6.org>, David Ahern <dsahern@...nel.org>, Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>, Dave Hansen <dave.hansen@...ux.intel.com>, <x86@...nel.org>, "H . Peter Anvin" <hpa@...or.com>, Jakub Kicinski <kuba@...nel.org>, Jesper Dangaard Brouer <hawk@...nel.org>, Russell King <rmk+kernel@...linux.org.uk>, James Morse <james.morse@....com>, Hou Tao <houtao1@...wei.com>, Jason Wang <wangborong@...rlc.com> Subject: Re: [PATCH bpf-next v7 4/4] bpf, arm64: bpf trampoline for arm64 On 7/11/2022 7:57 PM, Jean-Philippe Brucker wrote: > On Fri, Jul 08, 2022 at 05:30:32AM -0400, Xu Kuohai wrote: >> +static void invoke_bpf_prog(struct jit_ctx *ctx, struct bpf_tramp_link *l, >> + int args_off, int retval_off, int run_ctx_off, >> + bool save_ret) >> +{ >> + u32 *branch; >> + u64 enter_prog; >> + u64 exit_prog; >> + u8 r0 = bpf2a64[BPF_REG_0]; >> + struct bpf_prog *p = l->link.prog; >> + int cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); >> + >> + if (p->aux->sleepable) { >> + enter_prog = (u64)__bpf_prog_enter_sleepable; >> + exit_prog = (u64)__bpf_prog_exit_sleepable; >> + } else { >> + enter_prog = (u64)__bpf_prog_enter; >> + exit_prog = (u64)__bpf_prog_exit; >> + } >> + >> + if (l->cookie == 0) { >> + /* if cookie is zero, one instruction is enough to store it */ >> + emit(A64_STR64I(A64_ZR, A64_SP, run_ctx_off + cookie_off), ctx); >> + } else { >> + emit_a64_mov_i64(A64_R(10), l->cookie, ctx); >> + emit(A64_STR64I(A64_R(10), A64_SP, run_ctx_off + cookie_off), >> + ctx); >> + } >> + >> + /* save p to callee saved register x19 to avoid loading p with mov_i64 >> + * each time. >> + */ >> + emit_addr_mov_i64(A64_R(19), (const u64)p, ctx); >> + >> + /* arg1: prog */ >> + emit(A64_MOV(1, A64_R(0), A64_R(19)), ctx); >> + /* arg2: &run_ctx */ >> + emit(A64_ADD_I(1, A64_R(1), A64_SP, run_ctx_off), ctx); >> + >> + emit_call(enter_prog, ctx); >> + >> + /* if (__bpf_prog_enter(prog) == 0) >> + * goto skip_exec_of_prog; >> + */ >> + branch = ctx->image + ctx->idx; >> + emit(A64_NOP, ctx); >> + >> + /* save return value to callee saved register x20 */ >> + emit(A64_MOV(1, A64_R(20), A64_R(0)), ctx); >> + >> + emit(A64_ADD_I(1, A64_R(0), A64_SP, args_off), ctx); >> + if (!p->jited) >> + emit_addr_mov_i64(A64_R(1), (const u64)p->insnsi, ctx); >> + >> + emit_call((const u64)p->bpf_func, ctx); >> + >> + /* store return value, which is held in r0 for JIT and in x0 >> + * for interpreter. >> + */ >> + if (save_ret) >> + emit(A64_STR64I(p->jited ? r0 : A64_R(0), A64_SP, retval_off), >> + ctx); > > This should be only A64_R(0), not r0. r0 happens to equal A64_R(0) when > jitted due to the way build_epilogue() builds the function at the moment, > but we shouldn't rely on that. > looks like I misunderstood something, will change it to: /* store return value, which is held in x0 for interpreter and in * bpf register r0 for JIT, but r0 happens to equal x0 due to the * way build_epilogue() builds the JIT image. */ if (save_ret) emit(A64_STR64I(A64_R(0), A64_SP, retval_off), ctx); > Apart from that, for the series > > Reviewed-by: Jean-Philippe Brucker <jean-philippe@...aro.org> > > .
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