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Message-ID: <87757a16-60ad-1228-36d3-8eb640fde392@nvidia.com>
Date:   Thu, 21 Jul 2022 11:43:46 +0300
From:   Yishai Hadas <yishaih@...dia.com>
To:     "Tian, Kevin" <kevin.tian@...el.com>,
        "alex.williamson@...hat.com" <alex.williamson@...hat.com>,
        "jgg@...dia.com" <jgg@...dia.com>
CC:     "saeedm@...dia.com" <saeedm@...dia.com>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "Martins, Joao" <joao.m.martins@...cle.com>,
        "leonro@...dia.com" <leonro@...dia.com>,
        "maorg@...dia.com" <maorg@...dia.com>,
        "cohuck@...hat.com" <cohuck@...hat.com>
Subject: Re: [PATCH V2 vfio 01/11] net/mlx5: Introduce ifc bits for page
 tracker

On 21/07/2022 11:28, Tian, Kevin wrote:
>> From: Yishai Hadas <yishaih@...dia.com>
>> Sent: Thursday, July 14, 2022 4:13 PM
>> @@ -1711,7 +1712,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
>>   	u8         max_geneve_tlv_options[0x8];
>>   	u8         reserved_at_568[0x3];
>>   	u8         max_geneve_tlv_option_data_len[0x5];
>> -	u8         reserved_at_570[0x10];
>> +	u8         reserved_at_570[0x9];
>> +	u8         adv_virtualization[0x1];
>> +	u8         reserved_at_57a[0x6];
>>
>>   	u8	   reserved_at_580[0xb];
> any reason why the two consecutive reserved fields cannot
> be merged into one?

This follows our convention in this file that each 32 bits are separated 
into a block to ease tracking.

Yishai

>
> 	u8	resered_at_57a[0x11];


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