| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <787a4a58-2900-9f06-bb41-2ae96f70b025@seco.com>
Date: Mon, 25 Jul 2022 16:02:13 -0400
From: Sean Anderson <sean.anderson@...o.com>
To: Camelia Alexandra Groza <camelia.groza@....com>,
"David S . Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Madalin Bucur <madalin.bucur@....com>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>
Cc: Paolo Abeni <pabeni@...hat.com>,
Eric Dumazet <edumazet@...gle.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Russell King <linux@...linux.org.uk>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Kishon Vijay Abraham I <kishon@...com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Leo Li <leoyang.li@....com>, Rob Herring <robh+dt@...nel.org>,
Shawn Guo <shawnguo@...nel.org>, Vinod Koul <vkoul@...nel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>
Subject: Re: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
bindings
On 7/22/22 8:41 AM, Camelia Alexandra Groza wrote:
>> -----Original Message-----
>> From: Sean Anderson <sean.anderson@...o.com>
>> Sent: Thursday, July 21, 2022 18:41
>> To: Camelia Alexandra Groza <camelia.groza@....com>; David S . Miller
>> <davem@...emloft.net>; Jakub Kicinski <kuba@...nel.org>; Madalin Bucur
>> <madalin.bucur@....com>; netdev@...r.kernel.org
>> Cc: Paolo Abeni <pabeni@...hat.com>; Eric Dumazet
>> <edumazet@...gle.com>; linux-arm-kernel@...ts.infradead.org; Russell
>> King <linux@...linux.org.uk>; linux-kernel@...r.kernel.org; Kishon Vijay
>> Abraham I <kishon@...com>; Krzysztof Kozlowski
>> <krzysztof.kozlowski+dt@...aro.org>; Leo Li <leoyang.li@....com>; Rob
>> Herring <robh+dt@...nel.org>; Shawn Guo <shawnguo@...nel.org>; Vinod
>> Koul <vkoul@...nel.org>; devicetree@...r.kernel.org; linux-
>> phy@...ts.infradead.org
>> Subject: Re: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
>> bindings
>>
>>
>>
>> On 7/21/22 10:20 AM, Camelia Alexandra Groza wrote:
>> >> -----Original Message-----
>> >> From: Sean Anderson <sean.anderson@...o.com>
>> >> Sent: Saturday, July 16, 2022 1:00
>> >> To: David S . Miller <davem@...emloft.net>; Jakub Kicinski
>> >> <kuba@...nel.org>; Madalin Bucur <madalin.bucur@....com>;
>> >> netdev@...r.kernel.org
>> >> Cc: Paolo Abeni <pabeni@...hat.com>; Eric Dumazet
>> >> <edumazet@...gle.com>; linux-arm-kernel@...ts.infradead.org; Russell
>> >> King <linux@...linux.org.uk>; linux-kernel@...r.kernel.org; Sean
>> Anderson
>> >> <sean.anderson@...o.com>; Kishon Vijay Abraham I <kishon@...com>;
>> >> Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>; Leo Li
>> >> <leoyang.li@....com>; Rob Herring <robh+dt@...nel.org>; Shawn Guo
>> >> <shawnguo@...nel.org>; Vinod Koul <vkoul@...nel.org>;
>> >> devicetree@...r.kernel.org; linux-phy@...ts.infradead.org
>> >> Subject: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
>> >> bindings
>> >>
>> >> This adds appropriate bindings for the macs which use the SerDes. The
>> >> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
>> >> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
>> >> no driver for this device (and as far as I know all you can do with the
>> >> 100MHz clocks is gate them), so I have chosen to model it as a single
>> >> fixed clock.
>> >>
>> >> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
>> >> This means that Lane A (what the driver thinks is lane 0) uses pins
>> >> SD1_TX3_P/N.
>> >>
>> >> Because this will break ethernet if the serdes is not enabled, enable
>> >> the serdes driver by default on Layerscape.
>> >>
>> >> Signed-off-by: Sean Anderson <sean.anderson@...o.com>
>> >> ---
>> >> Please let me know if there is a better/more specific config I can use
>> >> here.
>> >>
>> >> (no changes since v1)
>> >
>> > My LS1046ARDB hangs at boot with this patch right after the second SerDes
>> is probed,
>> > right before the point where the PCI host bridge is registered. I can get
>> around this
>> > either by disabling the second SerDes node from the device tree, or
>> disabling
>> > CONFIG_PCI_LAYERSCAPE at build.
>> >
>> > I haven't debugged it more but there seems to be an issue here.
>>
>> Hm. Do you have anything plugged into the PCIe/SATA slots? I haven't been
>> testing with
>> anything there. For now, it may be better to just leave it disabled.
>>
>> --Sean
>
> Yes, I have an Intel e1000 card plugged in.
>
> Camelia
>
Can you try the following patch? I was able to boot with PCI with it applied.
>From 71f4136f1bdda89009936a9c24561b60e0554859 Mon Sep 17 00:00:00 2001
From: Sean Anderson <sean.anderson@...o.com>
Date: Mon, 25 Jul 2022 16:01:16 -0400
Subject: [PATCH] arm64: dts: ls1046a: Fix missing PCIe lane
Signed-off-by: Sean Anderson <sean.anderson@...o.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0b3765cad383..3841ba274782 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -532,7 +532,7 @@ pcie-0 {
/* PCIe.1 x1 */
cfg-1 {
fsl,cfg = <0x1>;
- fsl,first-lane = <1>;
+ fsl,first-lane = <0>;
};
/* PCIe.1 x4 */
@@ -543,6 +543,14 @@ cfg-3 {
};
};
+ /* PCIe.2 x1 */
+ pcie-1 {
+ fsl,index = <1>;
+ fsl,proto = "pcie";
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <1>;
+ };
+
pcie-2 {
fsl,index = <2>;
fsl,proto = "pcie";
--
2.35.1.1320.gc452695387.dirty
Powered by blists - more mailing lists