netdev - Re: commit 65ac79e181 breaks our ksz9567

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Message-ID: <20220818112846.ghhiqody2lwuznci@bang-olufsen.dk>
Date:   Thu, 18 Aug 2022 11:28:46 +0000
From:   Alvin Šipraga <ALSI@...g-olufsen.dk>
To:     Rasmus Villemoes <rasmus.villemoes@...vas.dk>
CC:     Network Development <netdev@...r.kernel.org>,
        Arun Ramadoss <arun.ramadoss@...rochip.com>,
        Vladimir Oltean <olteanv@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        "David S. Miller" <davem@...emloft.net>
Subject: Re: commit 65ac79e181 breaks our ksz9567

Hi Rasmus,

On Thu, Aug 18, 2022 at 01:03:13PM +0200, Rasmus Villemoes wrote:
> We have a board in development which includes a ksz9567 switch, whose
> cpu port is connected to a lan7801 usb chip. This works fine up until
> 5.18, but is broken in 5.19. The kernel log contains
> 
>  ksz9477-switch 4-005f lan1 (uninitialized): validation of gmii with
> support 00000000,00000000,000062ff and advertisement
> 00000000,00000000,000062ff failed: -EINVAL
>  ksz9477-switch 4-005f lan1 (uninitialized): failed to connect to PHY:
> -EINVAL
>  ksz9477-switch 4-005f lan1 (uninitialized): error -22 setting up PHY
> for tree 0, switch 0, port 0
> 
> and similar lines for the other four ports.

I think this is because the phylink_get_caps callback does not set
PHY_INTERFACE_MODE_GMII for ports with integrated PHY, which is the
default interface mode for phylib.

You can try this and see if it works (not even compile tested):

---
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 92a500e1ccd2..0d8044f2bd38 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -453,9 +453,16 @@ void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
        if (dev->info->supports_rgmii[port])
                phy_interface_set_rgmii(config->supported_interfaces);
 
-       if (dev->info->internal_phy[port])
+       if (dev->info->internal_phy[port]) {
                __set_bit(PHY_INTERFACE_MODE_INTERNAL,
                          config->supported_interfaces);
+
+               /* GMII is the default interface mode for phylib, so
+                * we have to support it for ports with integrated PHY.
+                */
+               __set_bit(PHY_INTERFACE_MODE_GMII,
+                         config->supported_interfaces);
+       }
 }
 EXPORT_SYMBOL_GPL(ksz_phylink_get_caps);