netdev - Re: [PATCH 1/4] net: mediatek: sgmii: fix powering up the SGMII phy

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Date:   Tue, 23 Aug 2022 16:31:35 +0200
From:   Alexander 'lynxis' Couzens <lynxis@...0.eu>
To:     Paolo Abeni <pabeni@...hat.com>
Cc:     Felix Fietkau <nbd@....name>, John Crispin <john@...ozen.org>,
        Sean Wang <sean.wang@...iatek.com>,
        Mark Lee <Mark-MC.Lee@...iatek.com>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Daniel Golle <daniel@...rotopia.org>
Subject: Re: [PATCH 1/4] net: mediatek: sgmii: fix powering up the SGMII phy

Hi Paolo,

> On Sun, 2022-08-21 at 00:45 +0200, Alexander Couzens wrote:
> > There are cases when the SGMII_PHYA_PWD register contains 0x9 which
> > prevents SGMII from working. The SGMII still shows link but no
> > traffic can flow. Writing 0x0 to the PHYA_PWD register fix the
> > issue. 0x0 was taken from a good working state of the SGMII
> > interface.  
> 
> do you have access to register documentation? what does 0x9 actually
> mean? is the '0' value based on just empirical evaluation?

I don't have any documentation which describes 0x9.
The datasheet [1] only contains the PHYA_PWD (0x10) bit and the initial
value is 0x10. 0x0 value is based on a register readout without the
patch from a working state.

I've tested it on mt7622 and Daniel Golle on mt7986.

[1] MT7622 Reference Manual, v1.0, 2018-12-19, 1972 pages

Best,
lynxis