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Message-Id: <20220826154650.615582-6-maxime.chevallier@bootlin.com> Date: Fri, 26 Aug 2022 17:46:50 +0200 From: Maxime Chevallier <maxime.chevallier@...tlin.com> To: davem@...emloft.net, Rob Herring <robh+dt@...nel.org> Cc: Maxime Chevallier <maxime.chevallier@...tlin.com>, netdev@...r.kernel.org, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, thomas.petazzoni@...tlin.com, Andrew Lunn <andrew@...n.ch>, Florian Fainelli <f.fainelli@...il.com>, Heiner Kallweit <hkallweit1@...il.com>, Russell King <linux@...linux.org.uk>, linux-arm-kernel@...ts.infradead.org, Vladimir Oltean <vladimir.oltean@....com>, Luka Perkov <luka.perkov@...tura.hr>, Robert Marko <robert.marko@...tura.hr> Subject: [PATCH net-next v3 5/5] ARM: dts: qcom: ipq4019: Add description for the IPQESS Ethernet controller The Qualcomm IPQ4019 includes an internal 5 ports switch, which is connected to the CPU through the internal IPQESS Ethernet controller. This commit adds support for this internal interface, which is internally connected to a modified version of the QCA8K Ethernet switch. This Ethernet controller only support a specific internal interface mode for connection to the switch. Signed-off-by: Maxime Chevallier <maxime.chevallier@...tlin.com> --- V2->V3: - No Changes V1->V2: - Added clock and resets arch/arm/boot/dts/qcom-ipq4019.dtsi | 46 +++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index bb307b8f678c..8cf1c5e6724f 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -38,6 +38,7 @@ aliases { spi1 = &blsp1_spi2; i2c0 = &blsp1_i2c3; i2c1 = &blsp1_i2c4; + ethernet0 = &gmac; }; cpus { @@ -590,6 +591,51 @@ wifi1: wifi@...0000 { status = "disabled"; }; + gmac: ethernet@...0000 { + compatible = "qcom,ipq4019-ess-edma"; + reg = <0xc080000 0x8000>; + resets = <&gcc ESS_RESET>; + reset-names = "ess"; + clocks = <&gcc GCC_ESS_CLK>; + clock-names = "ess"; + interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>; + + status = "disabled"; + + phy-mode = "internal"; + }; + mdio: mdio@...00 { #address-cells = <1>; #size-cells = <0>; -- 2.37.2
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