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Message-Id: <20220826154650.615582-5-maxime.chevallier@bootlin.com> Date: Fri, 26 Aug 2022 17:46:49 +0200 From: Maxime Chevallier <maxime.chevallier@...tlin.com> To: davem@...emloft.net, Rob Herring <robh+dt@...nel.org> Cc: Maxime Chevallier <maxime.chevallier@...tlin.com>, netdev@...r.kernel.org, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, thomas.petazzoni@...tlin.com, Andrew Lunn <andrew@...n.ch>, Florian Fainelli <f.fainelli@...il.com>, Heiner Kallweit <hkallweit1@...il.com>, Russell King <linux@...linux.org.uk>, linux-arm-kernel@...ts.infradead.org, Vladimir Oltean <vladimir.oltean@....com>, Luka Perkov <luka.perkov@...tura.hr>, Robert Marko <robert.marko@...tura.hr> Subject: [PATCH net-next v3 4/5] net: dt-bindings: Introduce the Qualcomm IPQESS Ethernet controller Add the DT binding for the IPQESS Ethernet Controller. This is a simple controller, only requiring the phy-mode, interrupts, clocks, and possibly a MAC address setting. Signed-off-by: Maxime Chevallier <maxime.chevallier@...tlin.com> --- V2->V3: - Cleanup on reset and clock names V1->V2: - Fixed the example - Added reset and clocks - Removed generic ethernet attributes .../devicetree/bindings/net/qcom,ipqess.yaml | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/qcom,ipqess.yaml diff --git a/Documentation/devicetree/bindings/net/qcom,ipqess.yaml b/Documentation/devicetree/bindings/net/qcom,ipqess.yaml new file mode 100644 index 000000000000..38927d0659e3 --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,ipqess.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,ipqess.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ ESS EDMA Ethernet Controller + +maintainers: + - Maxime Chevallier <maxime.chevallier@...tlin.com> + +allOf: + - $ref: "ethernet-controller.yaml#" + +properties: + compatible: + const: qcom,ipq4019e-ess-edma + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 32 + description: One interrupt per tx and rx queue, with up to 16 queues. + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - phy-mode + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq4019.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + gmac: ethernet@...0000 { + compatible = "qcom,ipq4019-ess-edma"; + reg = <0xc080000 0x8000>; + resets = <&gcc ESS_RESET>; + clocks = <&gcc GCC_ESS_CLK>; + interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>; + + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + asym-pause; + }; + }; + +... -- 2.37.2
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