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Message-ID: <Ywy6o2d9j4Z7+WYX@lunn.ch> Date: Mon, 29 Aug 2022 15:09:55 +0200 From: Andrew Lunn <andrew@...n.ch> To: Anand Moon <anand@...eble.ai> Cc: Giuseppe Cavallaro <peppe.cavallaro@...com>, Alexandre Torgue <alexandre.torgue@...s.st.com>, Jose Abreu <joabreu@...opsys.com>, "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>, Sugar Zhang <sugar.zhang@...k-chips.com>, David Wu <david.wu@...k-chips.com>, Jagan Teki <jagan@...eble.ai>, netdev@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH 2/2] net: ethernet: stmicro: stmmac: dwmac-rk: Add rv1126 support On Mon, Aug 29, 2022 at 06:50:42AM +0000, Anand Moon wrote: > Rockchip RV1126 has GMAC 10/100/1000M ethernet controller > via RGMII and RMII interfaces are configured via M0 and M1 pinmux. > > This patch adds rv1126 support by adding delay lines of M0 and M1 > simultaneously. What does 'delay lines' mean with respect to RGMII? The RGMII signals need a 2ns delay between the clock and the data lines. There are three places this can happen: 1) In the PHY 2) Extra long lines on the PCB 3) In the MAC Generally, 1) is used, and controlled via phy-mode. A value of PHY_INTERFACE_MODE_RGMII_ID passed to the PHY driver means it will add these delays. You don't want both the MAC and the PHY adding delays. Andrew
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