lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 29 Aug 2022 15:09:55 +0200
From:   Andrew Lunn <>
To:     Anand Moon <>
Cc:     Giuseppe Cavallaro <>,
        Alexandre Torgue <>,
        Jose Abreu <>,
        "David S. Miller" <>,
        Eric Dumazet <>,
        Jakub Kicinski <>,
        Paolo Abeni <>,
        Maxime Coquelin <>,
        Sugar Zhang <>,
        David Wu <>,
        Jagan Teki <>,,,,
Subject: Re: [PATCH 2/2] net: ethernet: stmicro: stmmac: dwmac-rk: Add rv1126

On Mon, Aug 29, 2022 at 06:50:42AM +0000, Anand Moon wrote:
> Rockchip RV1126 has GMAC 10/100/1000M ethernet controller
> via RGMII and RMII interfaces are configured via M0 and M1 pinmux.
> This patch adds rv1126 support by adding delay lines of M0 and M1
> simultaneously.

What does 'delay lines' mean with respect to RGMII?

The RGMII signals need a 2ns delay between the clock and the data
lines. There are three places this can happen:

1) In the PHY
2) Extra long lines on the PCB
3) In the MAC

Generally, 1) is used, and controlled via phy-mode. A value of
PHY_INTERFACE_MODE_RGMII_ID passed to the PHY driver means it will add
these delays.

You don't want both the MAC and the PHY adding delays.


Powered by blists - more mailing lists