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Date:   Mon, 29 Aug 2022 13:00:36 -0500
From:   Jerry Ray <jerry.ray@...rochip.com>
To:     Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>, <netdev@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <UNGLinuxDriver@...rochip.com>,
        Jerry Ray <jerry.ray@...rochip.com>
Subject: [PATCH 1/2] net: dsa: LAN9303: Add basic support for LAN9354

Add initial BYTE_ORDER read to sync to improve driver robustness

The lan9303 expects two mdio read transactions back-to-back to read a 32-bit
register. The first read transaction causes the other half of the 32-bit
register to get latched.  The subsequent read returns the latched second half
of the 32-bit read. The BYTE_ORDER register is an exception to this rule. As
it is a constant value, there is no need to latch the second half. We read
this register first in case there were reads during the boot loader process
that might have occurred prior to this driver taking over ownership of
accessing this device.

This patch has been tested on the SAMA5D3-EDS with a LAN9303 RMII daughter
card.

Signed-off-by: Jerry Ray <jerry.ray@...rochip.com>
---
 drivers/net/dsa/lan9303-core.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/net/dsa/lan9303-core.c b/drivers/net/dsa/lan9303-core.c
index e03ff1f267bb..17ae02a56bfe 100644
--- a/drivers/net/dsa/lan9303-core.c
+++ b/drivers/net/dsa/lan9303-core.c
@@ -32,6 +32,7 @@
 #define LAN9303_INT_EN 0x17
 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27)
 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26)
+#define LAN9303_BYTE_ORDER 0x19
 #define LAN9303_HW_CFG 0x1D
 # define LAN9303_HW_CFG_READY BIT(27)
 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26)
@@ -847,9 +848,10 @@ static int lan9303_check_device(struct lan9303 *chip)
 	int ret;
 	u32 reg;
 
-	ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, &reg);
+	// Dummy read to ensure MDIO access is in 32-bit sync.
+	ret = lan9303_read(chip->regmap, LAN9303_BYTE_ORDER, &reg);
 	if (ret) {
-		dev_err(chip->dev, "failed to read chip revision register: %d\n",
+		dev_err(chip->dev, "failed to access the device: %d\n",
 			ret);
 		if (!chip->reset_gpio) {
 			dev_dbg(chip->dev,
@@ -858,6 +860,13 @@ static int lan9303_check_device(struct lan9303 *chip)
 		return ret;
 	}
 
+	ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, &reg);
+	if (ret) {
+		dev_err(chip->dev, "failed to read chip revision register: %d\n",
+			ret);
+		return ret;
+	}
+
 	if ((reg >> 16) != LAN9303_CHIP_ID) {
 		dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n",
 			reg >> 16);
-- 
2.17.1

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