lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Thu, 1 Sep 2022 14:32:46 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Arun.Ramadoss@...rochip.com
Cc:     olteanv@...il.com, linux-kernel@...r.kernel.org,
        UNGLinuxDriver@...rochip.com, vivien.didelot@...il.com,
        linux@...linux.org.uk, Tristram.Ha@...rochip.com,
        f.fainelli@...il.com, kuba@...nel.org, edumazet@...gle.com,
        pabeni@...hat.com, netdev@...r.kernel.org,
        Woojung.Huh@...rochip.com, davem@...emloft.net
Subject: Re: [RFC Patch net-next v3 3/3] net: dsa: microchip: lan937x: add
 interrupt support for port phy link

> > > +static irqreturn_t lan937x_girq_thread_fn(int irq, void *dev_id)
> > > +{
> > > +     struct ksz_device *dev = dev_id;
> > > +     unsigned int nhandled = 0;
> > > +     unsigned int sub_irq;
> > > +     unsigned int n;
> > > +     u32 data;
> > > +     int ret;
> > > +
> > > +     ret = ksz_read32(dev, REG_SW_INT_STATUS__4, &data);
> > > +     if (ret)
> > > +             goto out;
> > > +
> > > +     if (data & POR_READY_INT) {
> > > +             ret = ksz_write32(dev, REG_SW_INT_STATUS__4,
> > > POR_READY_INT);
> > > +             if (ret)
> > > +                     goto out;
> > > +     }
> > 
> > What do these two read/writes do? It seems like you are discarding an
> > interrupt?
> 
> This interrupt in Power on reset interrupt. It is enabled by default in
> the chip. I am not performing any operation based on POR. So I just
> cleared the interrupt. Do I need to disable the POR interrupt in the
> setup function, since no operation is performed based on it?

It is pretty normal during interrupt controller creation to first
disable all interrupt sources, then clear the interrupt status
register if that can be done with a single operation, and then
register the interrupt controller with the IRQ core. That way, any
outstanding interrupts don't fire.

	    Andrew

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ