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Message-ID: <8fed012c-a683-89d8-0738-a3ea66412892@gmail.com>
Date: Wed, 7 Sep 2022 08:29:55 +0200
From: Mattias Forsblad <mattias.forsblad@...il.com>
To: Florian Fainelli <f.fainelli@...il.com>, netdev@...r.kernel.org
Cc: Andrew Lunn <andrew@...n.ch>,
Vivien Didelot <vivien.didelot@...il.com>,
Vladimir Oltean <olteanv@...il.com>,
"David S . Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>
Subject: Re: [PATCH net-next v4 1/6] net: dsa: mv88e6xxx: Add RMU enable for
select switches.
On 2022-09-06 23:46, Florian Fainelli wrote:
>
>
> On 9/5/2022 11:34 PM, Mattias Forsblad wrote:
>> Add RMU enable functionality for some Marvell SOHO switches.
>>
>> Signed-off-by: Mattias Forsblad <mattias.forsblad@...il.com>
>> ---
>
> [snip]
>
>> +int mv88e6085_g1_rmu_enable(struct mv88e6xxx_chip *chip, int upstream_port)
>> +{
>> + int val = MV88E6352_G1_CTL2_RMU_MODE_DISABLED;
>> +
>> + dev_dbg(chip->dev, "RMU: Enabling on port %d", upstream_port);
>
> This debug print is in every chip-specific function, so maybe you can consider moving it to mv88e6xxx_master_change()?
>
Ofc, will fix.
>> +
>> + switch (upstream_port) {
>> + case 9:
>> + val = MV88E6085_G1_CTL2_RM_ENABLE;
>> + break;
>> + case 10:
>> + val = MV88E6085_G1_CTL2_RM_ENABLE | MV88E6085_G1_CTL2_P10RM;
>> + break;
>> + default:
>> + return -EOPNOTSUPP;
>> + }
>> +
>> + return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
>> + MV88E6085_G1_CTL2_RM_ENABLE, val);
>> +}
>> +
>> int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
>> {
>> return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
>> MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
>> }
>> +int mv88e6352_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port)
>
> Can we name this argument upstream_port and pass it a dsa_switch_upstream_port() port already?
Will fix.
Mattias
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