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Date: Sat, 10 Sep 2022 13:24:12 +0530 From: Naveen Mamindlapalli <naveenm@...vell.com> To: <kuba@...nel.org>, <davem@...emloft.net>, <edumazet@...gle.com>, <pabeni@...hat.com>, <richardcochran@...il.com>, <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <sgoutham@...vell.com>, <hkelam@...vell.com> CC: Naveen Mamindlapalli <naveenm@...vell.com> Subject: [net-next PATCH 0/4] Add PTP support for CN10K silicon This patchset adds PTP support for CN10K silicon, specifically to workaround few hardware issues and to add 1-step mode. Patchset overview: Patch #1 returns correct ptp timestamp in nanoseconds captured when external timestamp event occurs. Patch #2 adds 1-step mode support. Patch #3 implements software workaround to generate PPS output properly. Patch #4 provides a software workaround for the rollover register default value, which causes ptp to return the wrong timestamp. Hariprasad Kelam (1): octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon Naveen Mamindlapalli (3): octeontx2-af: return correct ptp timestamp for CN10K silicon octeontx2-af: Add PTP PPS Errata workaround on CN10K silicon octeontx2-af: Initialize PTP_SEC_ROLLOVER register properly drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 2 + drivers/net/ethernet/marvell/octeontx2/af/ptp.c | 106 +++++++++++++++++++- drivers/net/ethernet/marvell/octeontx2/af/ptp.h | 3 + drivers/net/ethernet/marvell/octeontx2/af/rpm.c | 19 +++- drivers/net/ethernet/marvell/octeontx2/af/rpm.h | 5 + .../net/ethernet/marvell/octeontx2/af/rvu_nix.c | 8 +- .../net/ethernet/marvell/octeontx2/af/rvu_reg.h | 1 + .../ethernet/marvell/octeontx2/nic/otx2_common.h | 13 +++ .../ethernet/marvell/octeontx2/nic/otx2_ethtool.c | 8 +- .../net/ethernet/marvell/octeontx2/nic/otx2_pf.c | 11 +++ .../net/ethernet/marvell/octeontx2/nic/otx2_ptp.c | 103 ++++++++++++++----- .../ethernet/marvell/octeontx2/nic/otx2_struct.h | 11 ++- .../net/ethernet/marvell/octeontx2/nic/otx2_txrx.c | 110 ++++++++++++++++++++- 13 files changed, 359 insertions(+), 41 deletions(-) -- 2.16.5
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