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Date: Sat, 10 Sep 2022 13:24:16 +0530 From: Naveen Mamindlapalli <naveenm@...vell.com> To: <kuba@...nel.org>, <davem@...emloft.net>, <edumazet@...gle.com>, <pabeni@...hat.com>, <richardcochran@...il.com>, <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <sgoutham@...vell.com>, <hkelam@...vell.com> CC: Naveen Mamindlapalli <naveenm@...vell.com> Subject: [net-next PATCH 4/4] octeontx2-af: Initialize PTP_SEC_ROLLOVER register properly Since the reset value of PTP_SEC_ROLLOVER is incorrect on CNF10KB silicon, the ptp timestamps are inaccurate. This patch initializes the PTP_SEC_ROLLOVER register properly for the CNF10KB silicon. Signed-off-by: Naveen Mamindlapalli <naveenm@...vell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@...vell.com> --- drivers/net/ethernet/marvell/octeontx2/af/ptp.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c index 01f7dbad6b92..3411e2e47d46 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c @@ -52,12 +52,18 @@ #define PTP_CLOCK_COMP 0xF18ULL #define PTP_TIMESTAMP 0xF20ULL #define PTP_CLOCK_SEC 0xFD0ULL +#define PTP_SEC_ROLLOVER 0xFD8ULL #define CYCLE_MULT 1000 static struct ptp *first_ptp_block; static const struct pci_device_id ptp_id_table[]; +static bool is_ptp_dev_cnf10kb(struct ptp *ptp) +{ + return (ptp->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_B_PTP) ? true : false; +} + static bool is_ptp_dev_cn10k(struct ptp *ptp) { return (ptp->pdev->device == PCI_DEVID_CN10K_PTP) ? true : false; @@ -290,6 +296,10 @@ void ptp_start(struct ptp *ptp, u64 sclk, u32 ext_clk_freq, u32 extts) /* sclk is in MHz */ ptp->clock_rate = sclk * 1000000; + /* Program the seconds rollover value to 1 second */ + if (is_ptp_dev_cnf10kb(ptp)) + writeq(0x3b9aca00, ptp->reg_base + PTP_SEC_ROLLOVER); + /* Enable PTP clock */ clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); -- 2.16.5
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