netdev - Re: [net-next PATCH 0/4] Add PTP support for CN10K silicon

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <YxyiNLh4/0jSStwc@hoboy.vegasvil.org>
Date:   Sat, 10 Sep 2022 07:41:56 -0700
From:   Richard Cochran <richardcochran@...il.com>
To:     Naveen Mamindlapalli <naveenm@...vell.com>
Cc:     kuba@...nel.org, davem@...emloft.net, edumazet@...gle.com,
        pabeni@...hat.com, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, sgoutham@...vell.com,
        hkelam@...vell.com
Subject: Re: [net-next PATCH 0/4] Add PTP support for CN10K silicon

On Sat, Sep 10, 2022 at 01:24:12PM +0530, Naveen Mamindlapalli wrote:
> This patchset adds PTP support for CN10K silicon, specifically
> to workaround few hardware issues and to add 1-step mode.
> 
> Patchset overview:
> 
> Patch #1 returns correct ptp timestamp in nanoseconds captured
>          when external timestamp event occurs.
> 
> Patch #2 adds 1-step mode support.
> 
> Patch #3 implements software workaround to generate PPS output properly.
> 
> Patch #4 provides a software workaround for the rollover register default
>          value, which causes ptp to return the wrong timestamp.
> 
> Hariprasad Kelam (1):
>   octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
> 
> Naveen Mamindlapalli (3):
>   octeontx2-af: return correct ptp timestamp for CN10K silicon
>   octeontx2-af: Add PTP PPS Errata workaround on CN10K silicon
>   octeontx2-af: Initialize PTP_SEC_ROLLOVER register properly

For the series:

Acked-by: Richard Cochran <richardcochran@...il.com>