lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <OS0PR01MB5922461A6822870B79145DF686479@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Date:   Tue, 13 Sep 2022 19:17:28 +0000
From:   Biju Das <biju.das.jz@...renesas.com>
To:     Sergey Shtylyov <s.shtylyov@....ru>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>
CC:     Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-renesas-soc@...r.kernel.org" 
        <linux-renesas-soc@...r.kernel.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Chris Paterson <Chris.Paterson2@...esas.com>,
        Biju Das <biju.das@...renesas.com>
Subject: RE: [PATCH net-next v2] ravb: Add RZ/G2L MII interface support

Hi Sergey Shtylyov,

Thanks for the feed back.

> Subject: Re: [PATCH net-next v2] ravb: Add RZ/G2L MII interface support
> 
> On 9/12/22 1:51 PM, Biju Das wrote:
> 
> > EMAC IP found on RZ/G2L Gb ethernet supports MII interface.
> > This patch adds support for selecting MII interface mode.
> >
> > Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> [...]
> 
> > diff --git a/drivers/net/ethernet/renesas/ravb.h
> > b/drivers/net/ethernet/renesas/ravb.h
> > index b980bce763d3..0c7c0d404dcb 100644
> > --- a/drivers/net/ethernet/renesas/ravb.h
> > +++ b/drivers/net/ethernet/renesas/ravb.h
> [...]
> > @@ -965,6 +966,10 @@ enum CXR31_BIT {
> >  	CXR31_SEL_LINK1	= 0x00000008,
> >  };
> >
> > +enum CXR35_BIT {
> > +	CXR35_SEL_MII	= 0x03E80002,
> 
>    I'd really prefer that SEL_XMII[1:0] and HALFCYC_CLKSW[15:0] fields to
> be explicitly spelled out here (as they are in the manual)...

OK , will add CXR35_HALFCYC_CLKSW_1000 and CXR35_SEL_XMII_MII.


Cheers,
Biju

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ