netdev - Re: [PATCH net-next 01/12] arm64: dts: mediatek: mt7986: add support for Wireless Ethernet Dispatch

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Message-ID: <20220913120950.GA3397630-robh@kernel.org>
Date:   Tue, 13 Sep 2022 07:09:50 -0500
From:   Rob Herring <robh@...nel.org>
To:     Lorenzo Bianconi <lorenzo@...nel.org>
Cc:     netdev@...r.kernel.org, nbd@....name, john@...ozen.org,
        sean.wang@...iatek.com, Mark-MC.Lee@...iatek.com,
        davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
        pabeni@...hat.com, matthias.bgg@...il.com,
        linux-mediatek@...ts.infradead.org, lorenzo.bianconi@...hat.com,
        Bo.Jiao@...iatek.com, sujuan.chen@...iatek.com,
        ryder.Lee@...iatek.com, evelyn.tsai@...iatek.com,
        devicetree@...r.kernel.org
Subject: Re: [PATCH net-next 01/12] arm64: dts: mediatek: mt7986: add support
 for Wireless Ethernet Dispatch

On Thu, Sep 08, 2022 at 09:33:35PM +0200, Lorenzo Bianconi wrote:
> Introduce wed0 and wed1 nodes in order to enable offloading forwarding
> between ethernet and wireless devices on the mt7986 chipset.
> 
> Co-developed-by: Bo Jiao <Bo.Jiao@...iatek.com>
> Signed-off-by: Bo Jiao <Bo.Jiao@...iatek.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@...nel.org>
> ---
>  arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> index e3a407d03551..419d056b8369 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> @@ -222,6 +222,25 @@ ethsys: syscon@...00000 {
>  			 #reset-cells = <1>;
>  		};
>  
> +		wed_pcie: wed_pcie@...03000 {
> +			compatible = "mediatek,wed";

This is undocumented. It needs a binding.

> +			reg = <0 0x10003000 0 0x10>;
> +		};
> +
> +		wed0: wed@...10000 {
> +			compatible = "mediatek,wed", "syscon";

Some are syscon's and some are not?

> +			reg = <0 0x15010000 0 0x1000>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		wed1: wed@...11000 {
> +			compatible = "mediatek,wed", "syscon";
> +			reg = <0 0x15011000 0 0x1000>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>  		eth: ethernet@...00000 {
>  			compatible = "mediatek,mt7986-eth";
>  			reg = <0 0x15100000 0 0x80000>;
> @@ -256,6 +275,7 @@ eth: ethernet@...00000 {
>  						 <&apmixedsys CLK_APMIXED_SGMPLL>;
>  			mediatek,ethsys = <&ethsys>;
>  			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
> +			mediatek,wed = <&wed0>, <&wed1>;
>  			#reset-cells = <1>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> -- 
> 2.37.3
> 
>