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Date: Thu, 15 Sep 2022 01:39:42 +0200 From: Matej Vasilevski <matej.vasilevski@...nam.cz> To: Pavel Pisa <pisa@....felk.cvut.cz>, Ondrej Ille <ondrej.ille@...il.com>, Wolfgang Grandegger <wg@...ndegger.com>, Marc Kleine-Budde <mkl@...gutronix.de>, "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org> Cc: linux-can@...r.kernel.org, netdev@...r.kernel.org, devicetree@...r.kernel.org, Matej Vasilevski <matej.vasilevski@...nam.cz> Subject: [PATCH v4 1/3] dt-bindings: can: ctucanfd: add another clock for HW timestamping Add second clock phandle to specify the timestamping clock. Signed-off-by: Matej Vasilevski <matej.vasilevski@...nam.cz> --- .../bindings/net/can/ctu,ctucanfd.yaml | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml index 4635cb96fc64..432f0e3ed828 100644 --- a/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml +++ b/Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml @@ -44,9 +44,19 @@ properties: clocks: description: | - phandle of reference clock (100 MHz is appropriate - for FPGA implementation on Zynq-7000 system). - maxItems: 1 + Phandle of reference clock (100 MHz is appropriate for FPGA + implementation on Zynq-7000 system). Optionally add a phandle to + the timestamping clock connected to timestamping counter, if used. + minItems: 1 + items: + - description: core clock + - description: timestamping clock + + clock-names: + minItems: 1 + items: + - const: core-clk + - const: ts-clk required: - compatible @@ -61,6 +71,7 @@ examples: ctu_can_fd_0: can@...30000 { compatible = "ctu,ctucanfd"; interrupts = <0 30 4>; - clocks = <&clkc 15>; + clocks = <&clkc 15>, <&clkc 16>; + clock-names = "core-clk", "ts-clk"; reg = <0x43c30000 0x10000>; }; -- 2.25.1
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