netdev - Re: [PATCH v1 net-next 1/2] net: mscc: ocelot: utilize readx_poll

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <YyT76OIgNiJBH1Dm@euler>
Date:   Fri, 16 Sep 2022 15:42:48 -0700
From:   Colin Foster <colin.foster@...advantage.com>
To:     linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Cc:     Paolo Abeni <pabeni@...hat.com>, Jakub Kicinski <kuba@...nel.org>,
        Eric Dumazet <edumazet@...gle.com>,
        "David S. Miller" <davem@...emloft.net>,
        UNGLinuxDriver@...rochip.com,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Claudiu Manoil <claudiu.manoil@....com>,
        Vladimir Oltean <vladimir.oltean@....com>
Subject: Re: [PATCH v1 net-next 1/2] net: mscc: ocelot: utilize
 readx_poll_timeout() for chip reset

On Fri, Sep 16, 2022 at 12:13:48PM -0700, Colin Foster wrote:
> Clean up the reset code by utilizing readx_poll_timeout instead of a custom
> loop.
> 
> Signed-off-by: Colin Foster <colin.foster@...advantage.com>
> ---
>  drivers/net/ethernet/mscc/ocelot_vsc7514.c | 32 ++++++++++++++++------
>  1 file changed, 23 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c
> index ae42bbba5747..79b7af36b4f4 100644
> --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c
> +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c
> @@ -6,6 +6,7 @@
>   */
>  #include <linux/dsa/ocelot.h>
>  #include <linux/interrupt.h>
> +#include <linux/iopoll.h>
>  #include <linux/module.h>
>  #include <linux/of_net.h>
>  #include <linux/netdevice.h>
> @@ -25,6 +26,9 @@
>  #define VSC7514_VCAP_POLICER_BASE			128
>  #define VSC7514_VCAP_POLICER_MAX			191
>  
> +#define MEM_INIT_SLEEP_US				1000
> +#define MEM_INIT_TIMEOUT_US				100000
> +
>  static const u32 *ocelot_regmap[TARGET_MAX] = {
>  	[ANA] = vsc7514_ana_regmap,
>  	[QS] = vsc7514_qs_regmap,
> @@ -191,22 +195,32 @@ static const struct of_device_id mscc_ocelot_match[] = {
>  };
>  MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
>  
> +static int ocelot_mem_init_status(struct ocelot *ocelot)
> +{
> +	unsigned int val;
> +	int err;
> +
> +	err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
> +				&val);
> +
> +	return err ?: val;
> +}
> +
>  static int ocelot_reset(struct ocelot *ocelot)
>  {
> -	int retries = 100;
> +	int err;
>  	u32 val;
>  
>  	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
>  	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
>  
> -	do {
> -		msleep(1);
> -		regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
> -				  &val);
> -	} while (val && --retries);
> -
> -	if (!retries)
> -		return -ETIMEDOUT;
> +	/* MEM_INIT is a self-clearing bit. Wait for it to be cleared (should be
> +	 * 100us) before enabling the switch core.
> +	 */
> +	err = readx_poll_timeout(ocelot_mem_init_status, ocelot, val, !val,
> +				 MEM_INIT_SLEEP_US, MEM_INIT_TIMEOUT_US);
> +	if (IS_ERR_VALUE(err))

I see patchwork is complaining about IS_ERR_VALUE. I think it should
just be if (err). I'll test before sending v2 after the weekend.

> +		return err;
>  
>  	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
>  	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
> -- 
> 2.25.1
>