lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <TYBPR01MB534149AC78A0014DFCA587ABD84F9@TYBPR01MB5341.jpnprd01.prod.outlook.com>
Date:   Wed, 21 Sep 2022 07:54:21 +0000
From:   Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>
To:     Andrew Lunn <andrew@...n.ch>
CC:     "davem@...emloft.net" <davem@...emloft.net>,
        "edumazet@...gle.com" <edumazet@...gle.com>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "pabeni@...hat.com" <pabeni@...hat.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "geert+renesas@...der.be" <geert+renesas@...der.be>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-renesas-soc@...r.kernel.org" 
        <linux-renesas-soc@...r.kernel.org>
Subject: RE: [PATCH 5/5] arm64: dts: renesas: r8a779f0: spider: Enable
 Ethernet Switch

Hi Andrew,

> From: Andrew Lunn, Sent: Wednesday, September 14, 2022 9:14 PM
> 
> > > > +		port@2 {
> > > > +			reg = <2>;
> > > > +			phy-handle = <&etha2>;
> > > > +			phy-mode = "sgmii";
> > > > +			#address-cells = <1>;
> > > > +			#size-cells = <0>;
> > > > +			etha2: ethernet-phy@2 {
> > > > +				reg = <3>;
> > > > +				compatible = "ethernet-phy-ieee802.3-c45";
> > > > +			};
> > > > +		};
> > >
> > > I find it interesting you have PHYs are address 1, 2, 3, even though
> > > they are on individual busses. Why pay for the extra pullup/down
> > > resistors when they could all have the same address?
> >
> > I don't know why. But, the board really configured such PHY addresses...
> 
> That is not wrong. It could be the hardware engineer is used to shared
> MDIO busses, and just copy/pasted an existing design, but then
> separated the busses?

It's possible.

> You might see actual customer boards putting all the PHYs on one MDIO
> bus, to save pins. Linux has no problem with that, the phy-handle can
> point anywhere.

I see.

> One last thought. Is there anything in the data sheet about the switch
> hardware directly talking the PHY?

Yes, the switch hardware can talk the PHY directly.

> Some of the Marvell switches can do
> that, but we disable that feature. The hardware has no idea what the
> PHY driver is doing, such as selecting different pages.

That's interesting.

Best regards,
Yoshihiro Shimoda

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ