lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <b7e44e61-4beb-7b94-01e5-d217c546114d@linaro.org>
Date:   Sat, 24 Sep 2022 11:17:56 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Gerhard Engleder <gerhard@...leder-embedded.com>,
        netdev@...r.kernel.org
Cc:     davem@...emloft.net, kuba@...nel.org, edumazet@...gle.com,
        pabeni@...hat.com, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, devicetree@...r.kernel.org
Subject: Re: [PATCH net-next v3 2/6] dt-bindings: net: tsnep: Allow additional
 interrupts

On 23/09/2022 22:29, Gerhard Engleder wrote:
> Additional TX/RX queue pairs require dedicated interrupts. Extend
> binding with additional interrupts.
> 
> Signed-off-by: Gerhard Engleder <gerhard@...leder-embedded.com>
> ---
>  .../bindings/net/engleder,tsnep.yaml          | 37 ++++++++++++++++++-
>  1 file changed, 36 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml
> index 37e08ee744a8..ce1f1bd413c2 100644
> --- a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml
> +++ b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml
> @@ -20,7 +20,23 @@ properties:
>      maxItems: 1
>  
>    interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 8
> +
> +  interrupt-names:
> +    minItems: 1
> +    maxItems: 8
> +    items:
> +      pattern: '^mac|txrx-[1-7]$'

No. The order of items must be fixed. Now you allow any combination,
which is exactly what we do not want.

> +    description:
> +      If more than one interrupt is available, then interrupts are
> +      identified by their names.

Not really. Interrupts are fixed, unless explicitly mentioned otherwise.

> +      "mac" is the main interrupt for basic MAC features and the first
> +      TX/RX queue pair. If only a single interrupt is available, then
> +      it is assumed that this interrupt is the "mac" interrupt.
> +      "txrx-[1-7]" are the interrupts for additional TX/RX queue pairs.
> +      These interrupt names shall start with index 1 and increment the
> +      index by 1 with every further TX/RX queue pair.

Skip last three sentences - they will become redundant after
implementing proper items.
>  
>    dma-coherent: true
>  
> @@ -78,4 +94,23 @@ examples:
>                  };
>              };
>          };

Missing line break.


Best regards,
Krzysztof

Powered by blists - more mailing lists