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Date:   Sun, 25 Sep 2022 17:29:24 -0700
From:   Colin Foster <>
Cc:     Russell King <>,
        Linus Walleij <>,,
        Alexandre Belloni <>,
        Claudiu Manoil <>,
        Lee Jones <>,
        Krzysztof Kozlowski <>,
        Rob Herring <>,
        Paolo Abeni <>,
        Jakub Kicinski <>,
        Eric Dumazet <>,
        "David S. Miller" <>,
        Vladimir Oltean <>,
        Florian Fainelli <>,
        Vivien Didelot <>,
        Andrew Lunn <>
Subject: [PATCH v3 net-next 10/14] mfd: ocelot: prepend resource size macros to be 32-bit

The *_RES_SIZE macros are initally <= 0x100. Future resource sizes will be
upwards of 0x200000 in size.

To keep things clean, fully align the RES_SIZE macros to 32-bit to do
nothing more than make the code more consistent.

Signed-off-by: Colin Foster <>

    * No change

    * New patch - broken out from a different one

 drivers/mfd/ocelot-core.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c
index 1816d52c65c5..013e83173062 100644
--- a/drivers/mfd/ocelot-core.c
+++ b/drivers/mfd/ocelot-core.c
@@ -34,16 +34,16 @@
 #define VSC7512_MIIM0_RES_START		0x7107009c
 #define VSC7512_MIIM1_RES_START		0x710700c0
-#define VSC7512_MIIM_RES_SIZE		0x024
+#define VSC7512_MIIM_RES_SIZE		0x00000024
 #define VSC7512_PHY_RES_START		0x710700f0
-#define VSC7512_PHY_RES_SIZE		0x004
+#define VSC7512_PHY_RES_SIZE		0x00000004
 #define VSC7512_GPIO_RES_START		0x71070034
-#define VSC7512_GPIO_RES_SIZE		0x06c
+#define VSC7512_GPIO_RES_SIZE		0x0000006c
 #define VSC7512_SIO_CTRL_RES_START	0x710700f8
-#define VSC7512_SIO_CTRL_RES_SIZE	0x100
+#define VSC7512_SIO_CTRL_RES_SIZE	0x00000100
 #define VSC7512_GCB_RST_SLEEP_US	100
 #define VSC7512_GCB_RST_TIMEOUT_US	100000

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