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Date:   Tue, 27 Sep 2022 21:58:37 +0200
From:   Gerhard Engleder <>
        Gerhard Engleder <>
Subject: [PATCH net-next v4 1/6] dt-bindings: net: tsnep: Allow dma-coherent

Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
of AXI master ports. Also cache coherent AXI master ports are available.
The property "dma-coherent" is used to signal that DMA is cache

Add "dma-coherent" property to allow the configuration of cache coherent

Signed-off-by: Gerhard Engleder <>
 Documentation/devicetree/bindings/net/engleder,tsnep.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml
index d0e1476e15b5..37e08ee744a8 100644
--- a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml
+++ b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml
@@ -22,6 +22,8 @@ properties:
     maxItems: 1
+  dma-coherent: true
   local-mac-address: true
   mac-address: true

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