[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20220927195842.44641-2-gerhard@engleder-embedded.com>
Date: Tue, 27 Sep 2022 21:58:37 +0200
From: Gerhard Engleder <gerhard@...leder-embedded.com>
To: netdev@...r.kernel.org
Cc: davem@...emloft.net, kuba@...nel.org, edumazet@...gle.com,
pabeni@...hat.com, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, devicetree@...r.kernel.org,
Gerhard Engleder <gerhard@...leder-embedded.com>
Subject: [PATCH net-next v4 1/6] dt-bindings: net: tsnep: Allow dma-coherent
Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
of AXI master ports. Also cache coherent AXI master ports are available.
The property "dma-coherent" is used to signal that DMA is cache
coherent.
Add "dma-coherent" property to allow the configuration of cache coherent
DMA.
Signed-off-by: Gerhard Engleder <gerhard@...leder-embedded.com>
---
Documentation/devicetree/bindings/net/engleder,tsnep.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml
index d0e1476e15b5..37e08ee744a8 100644
--- a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml
+++ b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml
@@ -22,6 +22,8 @@ properties:
interrupts:
maxItems: 1
+ dma-coherent: true
+
local-mac-address: true
mac-address: true
--
2.30.2
Powered by blists - more mailing lists