netdev - Re: [PATCH net-next v3 1/6] dt-bindings: net: tsnep: Allow dma-coherent

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Message-ID: <4498db5c-d2d7-2e99-9184-ce195f7c7fc8@linaro.org>
Date:   Wed, 28 Sep 2022 09:17:53 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Gerhard Engleder <gerhard@...leder-embedded.com>,
        netdev@...r.kernel.org
Cc:     davem@...emloft.net, kuba@...nel.org, edumazet@...gle.com,
        pabeni@...hat.com, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, devicetree@...r.kernel.org
Subject: Re: [PATCH net-next v3 1/6] dt-bindings: net: tsnep: Allow
 dma-coherent

On 26/09/2022 19:46, Gerhard Engleder wrote:
>> That would be okay, but please add answer to why you are making this change.
> 
> I already prepared it:
> 
> Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
> of AXI master ports. Also cache coherent AXI master ports are available.
> The property "dma-coherent" is used to signal that DMA is cache
> coherent.
> Add "dma-coherent" property to allow the configuration of cache coherent
> DMA.
> 

Sounds good, thanks.

Best regards,
Krzysztof