netdev - Re: [PATCH net-next v4 1/6] dt-bindings: net: tsnep: Allow dma-coherent

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Message-ID: <166454888495.285888.6881149802161547142.robh@kernel.org>
Date:   Fri, 30 Sep 2022 09:41:25 -0500
From:   Rob Herring <robh@...nel.org>
To:     Gerhard Engleder <gerhard@...leder-embedded.com>
Cc:     edumazet@...gle.com, robh+dt@...nel.org, davem@...emloft.net,
        devicetree@...r.kernel.org, pabeni@...hat.com,
        krzysztof.kozlowski+dt@...aro.org, kuba@...nel.org,
        netdev@...r.kernel.org
Subject: Re: [PATCH net-next v4 1/6] dt-bindings: net: tsnep: Allow
 dma-coherent

On Tue, 27 Sep 2022 21:58:37 +0200, Gerhard Engleder wrote:
> Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
> of AXI master ports. Also cache coherent AXI master ports are available.
> The property "dma-coherent" is used to signal that DMA is cache
> coherent.
> 
> Add "dma-coherent" property to allow the configuration of cache coherent
> DMA.
> 
> Signed-off-by: Gerhard Engleder <gerhard@...leder-embedded.com>
> ---
>  Documentation/devicetree/bindings/net/engleder,tsnep.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@...nel.org>