netdev - RE: [PATCH net-next v3 2/3] net: txgbe: Reset hardware

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Tue, 11 Oct 2022 14:02:23 +0800
From:   Jiawen Wu <jiawenwu@...stnetic.com>
To:     "'Andrew Lunn'" <andrew@...n.ch>
Cc:     <netdev@...r.kernel.org>, <mengyuanlou@...-swift.com>
Subject: RE: [PATCH net-next v3 2/3] net: txgbe: Reset hardware

On Tuesday, October 11, 2022 9:55 AM, Andrew Lunn wrote:
> > > So you have an IO barrier before and a read barrier afterwards.  So
> > > all i think you need is a
> > mb(), not a
> > > full rd32().
> > >
> > >    Andrew
> > >
> >
> > I think we need a readl(), because there are problems that sometimes
> > IO is not synchronized with flushing memory on some domestic cpu platforms.
> > It can become a serious problem, causing register error configurations.
> 
> So please document this as a comment in the code.
> 
> I also then start to wounder if more such flushes are needed, to handle this broken hardware.
> Do you have a detailed description of what actually goes wrong? Otherwise how do you know
> when such a flush is needed?
> 
>    Andrew
> 

We don't know the exact behavior of the platforms, but it works under this workaround. That is, read
the register once after the write operations.