netdev - Re: [PATCH RFC 2/3] net: phy: marvell10g: Add host interface speed configuration

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 19 Oct 2022 12:55:00 +0200
From:   Marek Behún <kabel@...nel.org>
To:     Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>
Cc:     linux@...linux.org.uk, andrew@...n.ch, hkallweit1@...il.com,
        davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
        pabeni@...hat.com, netdev@...r.kernel.org,
        linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH RFC 2/3] net: phy: marvell10g: Add host interface speed
 configuration

On Wed, 19 Oct 2022 12:48:39 +0200
Marek Behún <kabel@...nel.org> wrote:

> On Wed, 19 Oct 2022 17:50:51 +0900
> Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com> wrote:
> 
> > Add support for selecting host speed mode. For now, only support
> > 1000M bps.
> > 
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>
> > ---
> >  drivers/net/phy/marvell10g.c | 23 +++++++++++++++++++++++
> >  1 file changed, 23 insertions(+)
> > 
> > diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
> > index 383a9c9f36e5..daf3242c6078 100644
> > --- a/drivers/net/phy/marvell10g.c
> > +++ b/drivers/net/phy/marvell10g.c
> > @@ -101,6 +101,10 @@ enum {
> >  	MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS	= BIT(13),
> >  	MV_AN_21X0_SERDES_CTRL2_RUN_INIT	= BIT(15),
> >  
> > +	MV_MOD_CONF		= 0xf000,
> > +	MV_MOD_CONF_SPEED_MASK	= 0x00c0,
> > +	MV_MOD_CONF_SPEED_1000	= BIT(7),
> > +  
> 
> Where did you get these values from? My documentation says:
>   Mode Configuration
>   Device 31, Register 0xF000
>   Bits
>   7:6   Reserved  R/W  0x3  This must always be 11.

Ah, I see. Probably from the MTD API sources...
But the bits should be set to 0x3 after HW reset, which means 10 Gbps,
and this should not interfere with 1000 Mbps SGMII operation. Do you
really need to set this? Isn't setting the MACTYPE to SGMII sufficient?

Marek