netdev - [PATCH v2 net-next 1/6] arm64: dts: mediatek: mt7986: add support for RX Wireless Ethernet Dispatch

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <41d67d36481f3099f953a462a80e99a4fcd477dd.1666549145.git.lorenzo@kernel.org>
Date:   Sun, 23 Oct 2022 20:28:05 +0200
From:   Lorenzo Bianconi <lorenzo@...nel.org>
To:     netdev@...r.kernel.org
Cc:     nbd@....name, john@...ozen.org, sean.wang@...iatek.com,
        Mark-MC.Lee@...iatek.com, davem@...emloft.net, edumazet@...gle.com,
        kuba@...nel.org, pabeni@...hat.com, matthias.bgg@...il.com,
        linux-mediatek@...ts.infradead.org, lorenzo.bianconi@...hat.com,
        Bo.Jiao@...iatek.com, sujuan.chen@...iatek.com,
        ryder.Lee@...iatek.com, evelyn.tsai@...iatek.com,
        devicetree@...r.kernel.org, robh@...nel.org, daniel@...rotopia.org
Subject: [PATCH v2 net-next 1/6] arm64: dts: mediatek: mt7986: add support for RX Wireless Ethernet Dispatch

Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
Dispatch to offload traffic received by the wlan interface to lan/wan
one.

Co-developed-by: Sujuan Chen <sujuan.chen@...iatek.com>
Signed-off-by: Sujuan Chen <sujuan.chen@...iatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@...nel.org>
---
 arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 73 +++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index 72e0d9722e07..e3b05280dcb6 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/mt7986-clk.h>
 #include <dt-bindings/reset/mt7986-resets.h>
+#include <dt-bindings/reset/ti-syscon.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -76,6 +77,31 @@ wmcpu_emi: wmcpu-reserved@...00000 {
 			no-map;
 			reg = <0 0x4fc00000 0 0x00100000>;
 		};
+
+		wo_emi0: wo-emi0@...00000 {
+			reg = <0 0x4fd00000 0 0x40000>;
+			no-map;
+		};
+
+		wo_emi1: wo-emi1@...40000 {
+			reg = <0 0x4fd40000 0 0x40000>;
+			no-map;
+		};
+
+		wo_ilm0: wo-ilm0@...e0000 {
+			reg = <0 0x151e0000 0 0x8000>;
+			no-map;
+		};
+
+		wo_ilm1: wo-ilm1@...f0000 {
+			reg = <0 0x151f0000 0 0x8000>;
+			no-map;
+		};
+
+		wo_data: wo-data@...80000 {
+			reg = <0 0x4fd80000 0 0x240000>;
+			no-map;
+		};
 	};
 
 	timer {
@@ -226,6 +252,12 @@ ethsys: syscon@...00000 {
 			 reg = <0 0x15000000 0 0x1000>;
 			 #clock-cells = <1>;
 			 #reset-cells = <1>;
+
+			ethsysrst: reset-controller {
+				compatible = "ti,syscon-reset";
+				#reset-cells = <1>;
+				ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>;
+			};
 		};
 
 		wed_pcie: wed-pcie@...03000 {
@@ -240,6 +272,10 @@ wed0: wed@...10000 {
 			reg = <0 0x15010000 0 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_data>;
+			mediatek,wo-ccif = <&wo_ccif0>;
+			mediatek,wo-dlm = <&wo_dlm0>;
+			mediatek,wo-boot = <&wo_boot>;
 		};
 
 		wed1: wed@...11000 {
@@ -248,6 +284,43 @@ wed1: wed@...11000 {
 			reg = <0 0x15011000 0 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_data>;
+			mediatek,wo-ccif = <&wo_ccif1>;
+			mediatek,wo-dlm = <&wo_dlm1>;
+			mediatek,wo-boot = <&wo_boot>;
+		};
+
+		wo_ccif0: wo-ccif1@...a5000 {
+			compatible = "mediatek,mt7986-wo-ccif","syscon";
+			reg = <0 0x151a5000 0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		wo_ccif1: wo-ccif1@...ad000 {
+			compatible = "mediatek,mt7986-wo-ccif","syscon";
+			reg = <0 0x151ad000 0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		wo_dlm0: wo-dlm@...e8000 {
+			compatible = "mediatek,mt7986-wo-dlm";
+			reg = <0 0x151e8000 0 0x2000>;
+			resets = <&ethsysrst 0>;
+			reset-names = "wocpu_rst";
+		};
+
+		wo_dlm1: wo-dlm@...51f8000 {
+			compatible = "mediatek,mt7986-wo-dlm";
+			reg = <0 0x151f8000 0 0x2000>;
+			resets = <&ethsysrst 0>;
+			reset-names = "wocpu_rst";
+		};
+
+		wo_boot: wo-boot@...94000 {
+			compatible = "mediatek,mt7986-wo-boot","syscon";
+			reg = <0 0x15194000 0 0x1000>;
 		};
 
 		eth: ethernet@...00000 {
-- 
2.37.3