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Date: Mon, 31 Oct 2022 12:13:17 +0530 From: Raju Lakkaraju <Raju.Lakkaraju@...rochip.com> To: Vladimir Oltean <olteanv@...il.com> CC: <netdev@...r.kernel.org>, <davem@...emloft.net>, <kuba@...nel.org>, <linux-kernel@...r.kernel.org>, <Bryan.Whitehead@...rochip.com>, <edumazet@...gle.com>, <pabeni@...hat.com>, <UNGLinuxDriver@...rochip.com>, Andrew Lunn <andrew@...n.ch> Subject: Re: [PATCH net-next V4] net: lan743x: Add support to SGMII register dump for PCI11010/PCI11414 chips Hi Vladimir, Thank you for review comments. The 10/20/2022 03:20, Vladimir Oltean wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On Tue, Oct 18, 2022 at 11:44:25AM +0530, Raju Lakkaraju wrote: > > +static void lan743x_sgmii_regs(struct net_device *dev, void *p) > > +{ > > + struct lan743x_adapter *adp = netdev_priv(dev); > > + u32 *rb = p; > > + > > + rb[ETH_SR_VSMMD_DEV_ID1] = SGMII_RD(adp, VSPEC1, 0x0002); > > + rb[ETH_SR_VSMMD_DEV_ID2] = SGMII_RD(adp, VSPEC1, 0x0003); > > + rb[ETH_SR_VSMMD_PCS_ID1] = SGMII_RD(adp, VSPEC1, 0x0004); > > + rb[ETH_SR_VSMMD_PCS_ID2] = SGMII_RD(adp, VSPEC1, 0x0005); > > + rb[ETH_SR_VSMMD_STS] = SGMII_RD(adp, VSPEC1, 0x0008); > > + rb[ETH_SR_VSMMD_CTRL] = SGMII_RD(adp, VSPEC1, 0x0009); > > + rb[ETH_SR_MII_CTRL] = SGMII_RD(adp, VSPEC2, 0x0000); > > + rb[ETH_SR_MII_STS] = SGMII_RD(adp, VSPEC2, 0x0001); > > + rb[ETH_SR_MII_DEV_ID1] = SGMII_RD(adp, VSPEC2, 0x0002); > > + rb[ETH_SR_MII_DEV_ID2] = SGMII_RD(adp, VSPEC2, 0x0003); > > + rb[ETH_SR_MII_AN_ADV] = SGMII_RD(adp, VSPEC2, 0x0004); > > + rb[ETH_SR_MII_LP_BABL] = SGMII_RD(adp, VSPEC2, 0x0005); > > + rb[ETH_SR_MII_EXPN] = SGMII_RD(adp, VSPEC2, 0x0006); > > + rb[ETH_SR_MII_EXT_STS] = SGMII_RD(adp, VSPEC2, 0x000F); > > + rb[ETH_SR_MII_TIME_SYNC_ABL] = SGMII_RD(adp, VSPEC2, 0x0708); > > + rb[ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_LWR] = SGMII_RD(adp, VSPEC2, 0x0709); > > + rb[ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_UPR] = SGMII_RD(adp, VSPEC2, 0x070A); > > + rb[ETH_SR_MII_TIME_SYNC_TX_MIN_DLY_LWR] = SGMII_RD(adp, VSPEC2, 0x070B); > > + rb[ETH_SR_MII_TIME_SYNC_TX_MIN_DLY_UPR] = SGMII_RD(adp, VSPEC2, 0x070C); > > + rb[ETH_SR_MII_TIME_SYNC_RX_MAX_DLY_LWR] = SGMII_RD(adp, VSPEC2, 0x070D); > > + rb[ETH_SR_MII_TIME_SYNC_RX_MAX_DLY_UPR] = SGMII_RD(adp, VSPEC2, 0x070E); > > + rb[ETH_SR_MII_TIME_SYNC_RX_MIN_DLY_LWR] = SGMII_RD(adp, VSPEC2, 0x070F); > > + rb[ETH_SR_MII_TIME_SYNC_RX_MIN_DLY_UPR] = SGMII_RD(adp, VSPEC2, 0x0710); > > + rb[ETH_VR_MII_DIG_CTRL1] = SGMII_RD(adp, VSPEC2, 0x8000); > > + rb[ETH_VR_MII_AN_CTRL] = SGMII_RD(adp, VSPEC2, 0x8001); > > + rb[ETH_VR_MII_AN_INTR_STS] = SGMII_RD(adp, VSPEC2, 0x8002); > > + rb[ETH_VR_MII_TC] = SGMII_RD(adp, VSPEC2, 0x8003); > > + rb[ETH_VR_MII_DBG_CTRL] = SGMII_RD(adp, VSPEC2, 0x8005); > > + rb[ETH_VR_MII_EEE_MCTRL0] = SGMII_RD(adp, VSPEC2, 0x8006); > > + rb[ETH_VR_MII_EEE_TXTIMER] = SGMII_RD(adp, VSPEC2, 0x8008); > > + rb[ETH_VR_MII_EEE_RXTIMER] = SGMII_RD(adp, VSPEC2, 0x8009); > > + rb[ETH_VR_MII_LINK_TIMER_CTRL] = SGMII_RD(adp, VSPEC2, 0x800A); > > + rb[ETH_VR_MII_EEE_MCTRL1] = SGMII_RD(adp, VSPEC2, 0x800B); > > + rb[ETH_VR_MII_DIG_STS] = SGMII_RD(adp, VSPEC2, 0x8010); > > + rb[ETH_VR_MII_ICG_ERRCNT1] = SGMII_RD(adp, VSPEC2, 0x8011); > > + rb[ETH_VR_MII_GPIO] = SGMII_RD(adp, VSPEC2, 0x8015); > > + rb[ETH_VR_MII_EEE_LPI_STATUS] = SGMII_RD(adp, VSPEC2, 0x8016); > > + rb[ETH_VR_MII_EEE_WKERR] = SGMII_RD(adp, VSPEC2, 0x8017); > > + rb[ETH_VR_MII_MISC_STS] = SGMII_RD(adp, VSPEC2, 0x8018); > > + rb[ETH_VR_MII_RX_LSTS] = SGMII_RD(adp, VSPEC2, 0x8020); > > + rb[ETH_VR_MII_GEN2_GEN4_TX_BSTCTRL0] = SGMII_RD(adp, VSPEC2, 0x8038); > > + rb[ETH_VR_MII_GEN2_GEN4_TX_LVLCTRL0] = SGMII_RD(adp, VSPEC2, 0x803A); > > + rb[ETH_VR_MII_GEN2_GEN4_TXGENCTRL0] = SGMII_RD(adp, VSPEC2, 0x803C); > > + rb[ETH_VR_MII_GEN2_GEN4_TXGENCTRL1] = SGMII_RD(adp, VSPEC2, 0x803D); > > + rb[ETH_VR_MII_GEN4_TXGENCTRL2] = SGMII_RD(adp, VSPEC2, 0x803E); > > + rb[ETH_VR_MII_GEN2_GEN4_TX_STS] = SGMII_RD(adp, VSPEC2, 0x8048); > > + rb[ETH_VR_MII_GEN2_GEN4_RXGENCTRL0] = SGMII_RD(adp, VSPEC2, 0x8058); > > + rb[ETH_VR_MII_GEN2_GEN4_RXGENCTRL1] = SGMII_RD(adp, VSPEC2, 0x8059); > > + rb[ETH_VR_MII_GEN4_RXEQ_CTRL] = SGMII_RD(adp, VSPEC2, 0x805B); > > + rb[ETH_VR_MII_GEN4_RXLOS_CTRL0] = SGMII_RD(adp, VSPEC2, 0x805D); > > + rb[ETH_VR_MII_GEN2_GEN4_MPLL_CTRL0] = SGMII_RD(adp, VSPEC2, 0x8078); > > + rb[ETH_VR_MII_GEN2_GEN4_MPLL_CTRL1] = SGMII_RD(adp, VSPEC2, 0x8079); > > + rb[ETH_VR_MII_GEN2_GEN4_MPLL_STS] = SGMII_RD(adp, VSPEC2, 0x8088); > > + rb[ETH_VR_MII_GEN2_GEN4_LVL_CTRL] = SGMII_RD(adp, VSPEC2, 0x8090); > > + rb[ETH_VR_MII_GEN4_MISC_CTRL2] = SGMII_RD(adp, VSPEC2, 0x8093); > > + rb[ETH_VR_MII_GEN2_GEN4_MISC_CTRL0] = SGMII_RD(adp, VSPEC2, 0x8099); > > + rb[ETH_VR_MII_GEN2_GEN4_MISC_CTRL1] = SGMII_RD(adp, VSPEC2, 0x809A); > > + rb[ETH_VR_MII_SNPS_CR_CTRL] = SGMII_RD(adp, VSPEC2, 0x80A0); > > + rb[ETH_VR_MII_SNPS_CR_ADDR] = SGMII_RD(adp, VSPEC2, 0x80A1); > > + rb[ETH_VR_MII_SNPS_CR_DATA] = SGMII_RD(adp, VSPEC2, 0x80A2); > > + rb[ETH_VR_MII_DIG_CTRL2] = SGMII_RD(adp, VSPEC2, 0x80E1); > > + rb[ETH_VR_MII_DIG_ERRCNT] = SGMII_RD(adp, VSPEC2, 0x80E2); > > What a nice DesignWare XPCS register layout... Is there any chance the > lan743x driver could use phylink and the XPCS driver from drivers/net/pcs/pcs-xpcs.c? Yes. I would like to use phylink for SFP support. I'm working on phylink. > I'm thinking it would be nice if we could all have access to a register > dump procedure for it somehow. Sure. I will check pcs-xpcs code and chnage regdump function after implement phylink. -------- Thanks, Raju
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