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Date: Mon, 31 Oct 2022 18:10:49 +0800
From: Chester Lin <clin@...e.com>
To: "David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Jan Petrous <jan.petrous@....com>
Cc: Chester Lin <clin@...e.com>, netdev@...r.kernel.org, s32@....com,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Andreas Färber <afaerber@...e.de>,
Matthias Brugger <mbrugger@...e.com>
Subject: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver
Add the DT schema for the DWMAC Ethernet controller on NXP S32 Common
Chassis.
Signed-off-by: Jan Petrous <jan.petrous@....com>
Signed-off-by: Chester Lin <clin@...e.com>
---
.../bindings/net/nxp,s32cc-dwmac.yaml | 145 ++++++++++++++++++
1 file changed, 145 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml
diff --git a/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml
new file mode 100644
index 000000000000..f6b8486f9d42
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021-2022 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/nxp,s32cc-dwmac.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NXP S32CC DWMAC Ethernet controller
+
+maintainers:
+ - Jan Petrous <jan.petrous@....com>
+ - Chester Lin <clin@...e.com>
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nxp,s32cc-dwmac
+ required:
+ - compatible
+
+allOf:
+ - $ref: "snps,dwmac.yaml#"
+
+properties:
+ compatible:
+ contains:
+ enum:
+ - nxp,s32cc-dwmac
+
+ reg:
+ items:
+ - description: Main GMAC registers
+ - description: S32 MAC control registers
+
+ dma-coherent:
+ description:
+ Declares GMAC device as DMA coherent
+
+ clocks:
+ items:
+ - description: Main GMAC clock
+ - description: Peripheral registers clock
+ - description: Transmit SGMII clock
+ - description: Transmit RGMII clock
+ - description: Transmit RMII clock
+ - description: Transmit MII clock
+ - description: Receive SGMII clock
+ - description: Receive RGMII clock
+ - description: Receive RMII clock
+ - description: Receive MII clock
+ - description:
+ PTP reference clock. This clock is used for programming the
+ Timestamp Addend Register. If not passed then the system
+ clock will be used.
+
+ clock-names:
+ items:
+ - const: stmmaceth
+ - const: pclk
+ - const: tx_sgmii
+ - const: tx_rgmii
+ - const: tx_rmii
+ - const: tx_mii
+ - const: rx_sgmii
+ - const: rx_rgmii
+ - const: rx_rmii
+ - const: rx_mii
+ - const: ptp_ref
+
+ tx-fifo-depth:
+ const: 20480
+
+ rx-fifo-depth:
+ const: 20480
+
+required:
+ - compatible
+ - reg
+ - tx-fifo-depth
+ - rx-fifo-depth
+ - clocks
+ - clock-names
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ #define S32GEN1_SCMI_CLK_GMAC0_AXI
+ #define S32GEN1_SCMI_CLK_GMAC0_TX_SGMII
+ #define S32GEN1_SCMI_CLK_GMAC0_TX_RGMII
+ #define S32GEN1_SCMI_CLK_GMAC0_TX_RMII
+ #define S32GEN1_SCMI_CLK_GMAC0_TX_MII
+ #define S32GEN1_SCMI_CLK_GMAC0_RX_SGMII
+ #define S32GEN1_SCMI_CLK_GMAC0_RX_RGMII
+ #define S32GEN1_SCMI_CLK_GMAC0_RX_RMII
+ #define S32GEN1_SCMI_CLK_GMAC0_RX_MII
+ #define S32GEN1_SCMI_CLK_GMAC0_TS
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gmac0: ethernet@...3c000 {
+ compatible = "nxp,s32cc-dwmac";
+ reg = <0x4033c000 0x2000>, /* gmac IP */
+ <0x4007C004 0x4>; /* S32 CTRL_STS reg */
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ phy-mode = "rgmii-id";
+ tx-fifo-depth = <20480>;
+ rx-fifo-depth = <20480>;
+ dma-coherent;
+ clocks = <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>,
+ <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>,
+ <&clks S32GEN1_SCMI_CLK_GMAC0_TX_SGMII>,
+ <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RGMII>,
+ <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RMII>,
+ <&clks S32GEN1_SCMI_CLK_GMAC0_TX_MII>,
+ <&clks S32GEN1_SCMI_CLK_GMAC0_RX_SGMII>,
+ <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RGMII>,
+ <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RMII>,
+ <&clks S32GEN1_SCMI_CLK_GMAC0_RX_MII>,
+ <&clks S32GEN1_SCMI_CLK_GMAC0_TS>;
+ clock-names = "stmmaceth", "pclk",
+ "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii",
+ "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii",
+ "ptp_ref";
+
+ gmac0_mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ ethernet-phy@4 {
+ reg = <0x04>;
+ };
+ };
+ };
+ };
--
2.37.3
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