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Message-Id: <20221101114806.1186516-1-vladimir.oltean@nxp.com>
Date: Tue, 1 Nov 2022 13:48:02 +0200
From: Vladimir Oltean <vladimir.oltean@....com>
To: netdev@...r.kernel.org
Cc: Claudiu Manoil <claudiu.manoil@....com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
UNGLinuxDriver@...rochip.com,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
Sean Anderson <sean.anderson@...o.com>,
Colin Foster <colin.foster@...advantage.com>,
Andrew Lunn <andrew@...n.ch>,
Vivien Didelot <vivien.didelot@...il.com>,
Florian Fainelli <f.fainelli@...il.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>
Subject: [PATCH net-next 0/4] Remove phylink_validate() from Felix DSA driver
The Felix DSA driver still uses its own phylink_validate() procedure
rather than the (relatively newly introduced) phylink_generic_validate()
because the latter did not cater for the case where a PHY provides rate
matching between the Ethernet cable side speed and the SERDES side
speed (and does not advertise other speeds except for the SERDES speed).
This changed with Sean Anderson's generic support for rate matching PHYs
in phylib and phylink:
https://patchwork.kernel.org/project/netdevbpf/cover/20220920221235.1487501-1-sean.anderson@seco.com/
Building upon that support, this patch set makes Linux understand that
the PHYs used in combination with the Felix DSA driver (SCH-30841 riser
card with AQR412 PHY, used with SERDES protocol 0x7777 - 4x2500base-x,
plugged into LS1028A-QDS) do support PAUSE rate matching. This requires
Aquantia PHY driver support for new PHY IDs.
To activate the rate matching support in phylink, config->mac_capabilities
must be populated. Coincidentally, this also opts the Felix driver into
the generic phylink validation.
Next, code that is no longer necessary is eliminated. This includes the
Felix driver validation procedures for VSC9959 and VSC9953, the
workaround in the Ocelot switch library to leave RX flow control always
enabled, as well as DSA plumbing necessary for a custom phylink
validation procedure to be propagated to the hardware driver level.
Many thanks go to Sean Anderson for providing generic support for rate
matching.
Vladimir Oltean (4):
net: phy: aquantia: add AQR112 and AQR412 PHY IDs
net: dsa: felix: use phylink_generic_validate()
net: mscc: ocelot: drop workaround for forcing RX flow control
net: dsa: remove phylink_validate() method
drivers/net/dsa/ocelot/felix.c | 16 +++-------
drivers/net/dsa/ocelot/felix.h | 3 --
drivers/net/dsa/ocelot/felix_vsc9959.c | 30 ------------------
drivers/net/dsa/ocelot/seville_vsc9953.c | 27 ----------------
drivers/net/ethernet/mscc/ocelot.c | 6 ++--
drivers/net/phy/aquantia_main.c | 40 ++++++++++++++++++++++++
include/net/dsa.h | 3 --
net/dsa/port.c | 18 +----------
8 files changed, 47 insertions(+), 96 deletions(-)
--
2.34.1
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