netdev - Re: [PATCH v5 net-next 3/3] net: axienet: set mdio clock according to bus-frequency

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Date:   Fri, 18 Nov 2022 01:07:38 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Andy Chiu <andy.chiu@...ive.com>
Cc:     davem@...emloft.net, kuba@...nel.org, michal.simek@...inx.com,
        radhey.shyam.pandey@...inx.com, netdev@...r.kernel.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        robh+dt@...nel.org, pabeni@...hat.com, edumazet@...gle.com,
        greentime.hu@...ive.com
Subject: Re: [PATCH v5 net-next 3/3] net: axienet: set mdio clock according
 to bus-frequency

On Thu, Nov 17, 2022 at 11:40:14PM +0800, Andy Chiu wrote:
> Some FPGA platforms have 80KHz MDIO bus frequency constraint when
> connecting Ethernet to its on-board external Marvell PHY. Thus, we may
> have to set MDIO clock according to the DT. Otherwise, use the default
> 2.5 MHz, as specified by 802.3, if the entry is not present.
> 
> Also, change MAX_MDIO_FREQ to DEFAULT_MDIO_FREQ because we may actually
> set MDIO bus frequency higher than 2.5MHz if undelying devices support
> it. And properly disable the mdio bus clock in error path.
> 
> Signed-off-by: Andy Chiu <andy.chiu@...ive.com>

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew