netdev - [PATCH v2 9/9] riscv: dts: starfive: visionfive-v2: Add phy clock delay train configuration

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Date:   Fri, 16 Dec 2022 15:06:32 +0800
From:   Yanhong Wang <yanhong.wang@...rfivetech.com>
To:     <linux-riscv@...ts.infradead.org>, <netdev@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC:     "David S . Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Emil Renner Berthing <kernel@...il.dk>,
        Richard Cochran <richardcochran@...il.com>,
        Andrew Lunn <andrew@...n.ch>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Peter Geis <pgwipeout@...il.com>,
        Yanhong Wang <yanhong.wang@...rfivetech.com>
Subject: [PATCH v2 9/9] riscv: dts: starfive: visionfive-v2: Add phy clock delay train configuration

In view of the particularity of StarFive JH7110 SoC, the PHY clock delay
train configuration parameters must be adjusted for StarFive VisionFive
v2 board.

Signed-off-by: Yanhong Wang <yanhong.wang@...rfivetech.com>
---
 .../jh7110-starfive-visionfive-v2.dts         | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
index c8946cf3a268..81329d67ef0f 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
@@ -15,6 +15,8 @@
 
 	aliases {
 		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
 	};
 
 	chosen {
@@ -114,3 +116,29 @@
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
+
+&gmac0 {
+	status = "okay";
+};
+
+&phy0 {
+	rxc_dly_en = <1>;
+	tx_delay_sel_fe = <5>;
+	tx_delay_sel = <0xa>;
+	tx_inverted_10 = <0x1>;
+	tx_inverted_100 = <0x1>;
+	tx_inverted_1000 = <0x1>;
+};
+
+&gmac1 {
+	status = "okay";
+};
+
+&phy1 {
+	rxc_dly_en = <0>;
+	tx_delay_sel_fe = <5>;
+	tx_delay_sel = <0>;
+	tx_inverted_10 = <0x1>;
+	tx_inverted_100 = <0x1>;
+	tx_inverted_1000 = <0x0>;
+};
-- 
2.17.1