netdev - Re: [Intel-wired-lan] [PATCH] igc: Mask replay rollover/timeout errors in I225

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Date:   Tue, 3 Jan 2023 13:13:23 -0600
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     "Khandelwal, Rajat" <rajat.khandelwal@...el.com>
Cc:     "Neftin, Sasha" <sasha.neftin@...el.com>,
        Paul Menzel <pmenzel@...gen.mpg.de>,
        Rajat Khandelwal <rajat.khandelwal@...ux.intel.com>,
        "Ruinskiy, Dima" <dima.ruinskiy@...el.com>,
        "Lifshits, Vitaly" <vitaly.lifshits@...el.com>,
        "naamax.meir" <naamax.meir@...ux.intel.com>,
        Leon Romanovsky <leon@...nel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "Mushayev, Nikolay" <nikolay.mushayev@...el.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "Brandeburg, Jesse" <jesse.brandeburg@...el.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "edumazet@...gle.com" <edumazet@...gle.com>,
        "Nguyen, Anthony L" <anthony.l.nguyen@...el.com>,
        "Efrati, Nir" <nir.efrati@...el.com>,
        "intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "pabeni@...hat.com" <pabeni@...hat.com>,
        "davem@...emloft.net" <davem@...emloft.net>
Subject: Re: [Intel-wired-lan] [PATCH] igc: Mask replay rollover/timeout
 errors in I225_LMVP

On Tue, Jan 03, 2023 at 06:58:36AM +0000, Khandelwal, Rajat wrote:
> ...
> The reason I masked inherently is I witnessed a function
> netxen_mask_aer_correctable() inside
> net/ethernet/qlogic/netxen/netxen_nic_main.c, which masks the
> correctable errors in the corresponding PCIe device.

In my opinion, netxen_mask_aer_correctable() should not exist.  The
PCI core should own the PCI_ERR_COR_MASK register.

netxen_mask_aer_correctable() was added by dce87b960cf4 ("netxen: mask
correctable error") with the note that it is a "HW workaround."  Maybe
it covers up some hardware defect in the device, although it doesn't
include any evidence of this.

But if we do actually need it, I would rather have the driver set a
quirk bit that the PCI core can use to mask correctable errors so the
AER configuration is all in one place.

Bjorn