Message-ID: <Y7xDDNMIDyHKLicG@zn.tnic>
Date:   Mon, 9 Jan 2023 17:38:36 +0100
From:   Borislav Petkov <bp@...en8.de>
To:     Michael Kelley <mikelley@...rosoft.com>
Cc:     hpa@...or.com, kys@...rosoft.com, haiyangz@...rosoft.com,
        wei.liu@...nel.org, decui@...rosoft.com, luto@...nel.org,
        peterz@...radead.org, davem@...emloft.net, edumazet@...gle.com,
        kuba@...nel.org, pabeni@...hat.com, lpieralisi@...nel.org,
        robh@...nel.org, kw@...ux.com, bhelgaas@...gle.com, arnd@...db.de,
        hch@...radead.org, m.szyprowski@...sung.com, robin.murphy@....com,
        thomas.lendacky@....com, brijesh.singh@....com, tglx@...utronix.de,
        mingo@...hat.com, dave.hansen@...ux.intel.com,
        Tianyu.Lan@...rosoft.com, kirill.shutemov@...ux.intel.com,
        sathyanarayanan.kuppuswamy@...ux.intel.com, ak@...ux.intel.com,
        isaku.yamahata@...el.com, dan.j.williams@...el.com,
        jane.chu@...cle.com, seanjc@...gle.com, tony.luck@...el.com,
        x86@...nel.org, linux-kernel@...r.kernel.org,
        linux-hyperv@...r.kernel.org, netdev@...r.kernel.org,
        linux-pci@...r.kernel.org, linux-arch@...r.kernel.org,
        iommu@...ts.linux.dev
Subject: Re: [Patch v4 06/13] x86/hyperv: Change vTOM handling to use
 standard coco mechanisms

On Thu, Dec 01, 2022 at 07:30:24PM -0800, Michael Kelley wrote:
> Hyper-V guests on AMD SEV-SNP hardware have the option of using the
> "virtual Top Of Memory" (vTOM) feature specified by the SEV-SNP
> architecture. With vTOM, shared vs. private memory accesses are
> controlled by splitting the guest physical address space into two
> halves.  vTOM is the dividing line where the uppermost bit of the
> physical address space is set; e.g., with 47 bits of guest physical
> address space, vTOM is 0x400000000000 (bit 46 is set).  Guest physical
> memory is accessible at two parallel physical addresses -- one below
> vTOM and one above vTOM.  Accesses below vTOM are private (encrypted)
> while accesses above vTOM are shared (decrypted). In this sense, vTOM
> is like the GPA.SHARED bit in Intel TDX.
> 
> Support for Hyper-V guests using vTOM was added to the Linux kernel in
> two patch sets[1][2]. This support treats the vTOM bit as part of
> the physical address. For accessing shared (decrypted) memory, these
> patch sets create a second kernel virtual mapping that maps to physical
> addresses above vTOM.
> 
> A better approach is to treat the vTOM bit as a protection flag, not
> as part of the physical address. This new approach is like the approach
> for the GPA.SHARED bit in Intel TDX. Rather than creating a second kernel
> virtual mapping, the existing mapping is updated using recently added
> coco mechanisms.  When memory is changed between private and shared using
> set_memory_decrypted() and set_memory_encrypted(), the PTEs for the
> existing kernel mapping are changed to add or remove the vTOM bit
> in the guest physical address, just as with TDX. The hypercalls to
> change the memory status on the host side are made using the existing
> callback mechanism. Everything just works, with a minor tweak to map
> the IO-APIC to use private accesses.
> 
> To accomplish the switch in approach, the following must be done in
> this single patch:

s/in this single patch//

> * Update Hyper-V initialization to set the cc_mask based on vTOM
>   and do other coco initialization.
> 
> * Update physical_mask so the vTOM bit is no longer treated as part
>   of the physical address
> 
> * Remove CC_VENDOR_HYPERV and merge the associated vTOM functionality
>   under CC_VENDOR_AMD. Update cc_mkenc() and cc_mkdec() to set/clear
>   the vTOM bit as a protection flag.
> 
> * Code already exists to make hypercalls to inform Hyper-V about pages
>   changing between shared and private.  Update this code to run as a
>   callback from __set_memory_enc_pgtable().
> 
> * Remove the Hyper-V special case from __set_memory_enc_dec()
> 
> * Remove the Hyper-V specific call to swiotlb_update_mem_attributes()
>   since mem_encrypt_init() will now do it.
> 
> [1] https://lore.kernel.org/all/20211025122116.264793-1-ltykernel@gmail.com/
> [2] https://lore.kernel.org/all/20211213071407.314309-1-ltykernel@gmail.com/
> 
> Signed-off-by: Michael Kelley <mikelley@...rosoft.com>
> ---
>  arch/x86/coco/core.c             | 37 ++++++++++++++++++++--------
>  arch/x86/hyperv/hv_init.c        | 11 ---------
>  arch/x86/hyperv/ivm.c            | 52 +++++++++++++++++++++++++++++++---------
>  arch/x86/include/asm/coco.h      |  1 -
>  arch/x86/include/asm/mshyperv.h  |  8 ++-----
>  arch/x86/include/asm/msr-index.h |  1 +
>  arch/x86/kernel/cpu/mshyperv.c   | 15 ++++++------
>  arch/x86/mm/pat/set_memory.c     |  3 ---
>  8 files changed, 78 insertions(+), 50 deletions(-)
> 
> diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c
> index 49b44f8..c361c52 100644
> --- a/arch/x86/coco/core.c
> +++ b/arch/x86/coco/core.c
> @@ -44,6 +44,24 @@ static bool intel_cc_platform_has(enum cc_attr attr)
>  static bool amd_cc_platform_has(enum cc_attr attr)
>  {
>  #ifdef CONFIG_AMD_MEM_ENCRYPT
> +
> +	/*
> +	 * Handle the SEV-SNP vTOM case where sme_me_mask must be zero,
> +	 * and the other levels of SME/SEV functionality, including C-bit
> +	 * based SEV-SNP, must not be enabled.
> +	 */
> +	if (sev_status & MSR_AMD64_SNP_VTOM_ENABLED) {

		return amd_cc_platform_vtom();

or so and then stick that switch in there.

This way it looks kinda grafted in front and with a function call with a telling
name it says it is a special case...

> +		switch (attr) {
> +		case CC_ATTR_GUEST_MEM_ENCRYPT:
> +		case CC_ATTR_MEM_ENCRYPT:
> +		case CC_ATTR_ACCESS_IOAPIC_ENCRYPTED:
> +			return true;
> +		default:
> +			return false;
> +		}
> +	}

The rest looks kinda nice, I gotta say. I can't complain. :)

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Powered by blists - more mailing lists