netdev - Re: [PATCH v4 net-next 3/5] net: ethernet: mtk_eth_soc: align reset procedure to vendor sdk

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Date:   Wed, 11 Jan 2023 18:11:51 +0100
From:   Lorenzo Bianconi <lorenzo.bianconi@...hat.com>
To:     Lorenzo Bianconi <lorenzo@...nel.org>
Cc:     netdev@...r.kernel.org, davem@...emloft.net, edumazet@...gle.com,
        kuba@...nel.org, pabeni@...hat.com, nbd@....name, john@...ozen.org,
        sean.wang@...iatek.com, Mark-MC.Lee@...iatek.com,
        sujuan.chen@...iatek.com, daniel@...rotopia.org, leon@...nel.org
Subject: Re: [PATCH v4 net-next 3/5] net: ethernet: mtk_eth_soc: align reset
 procedure to vendor sdk

[...]

> -
> -	/* restart underlying hardware such as power, clock, pin mux
> -	 * and the connected phy
> -	 */
> -	mtk_hw_deinit(eth);

I missed a usleep_range here. Please drop this version, I will post v5 soon.

Regards,
Lorenzo

>  
>  	if (eth->dev->pins)
>  		pinctrl_select_state(eth->dev->pins->p,
> @@ -3801,15 +3841,19 @@ static void mtk_pending_work(struct work_struct *work)
>  	for (i = 0; i < MTK_MAC_COUNT; i++) {
>  		if (!test_bit(i, &restart))
>  			continue;
> -		err = mtk_open(eth->netdev[i]);
> -		if (err) {
> +
> +		if (mtk_open(eth->netdev[i])) {
>  			netif_alert(eth, ifup, eth->netdev[i],
> -			      "Driver up/down cycle failed, closing device.\n");
> +				    "Driver up/down cycle failed\n");
>  			dev_close(eth->netdev[i]);
>  		}
>  	}
>  
> -	dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
> +	/* enabe FE P3 and P4 */
> +	val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3;
> +	if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> +		val &= ~MTK_FE_LINK_DOWN_P4;
> +	mtk_w32(eth, val, MTK_FE_GLO_CFG);
>  
>  	clear_bit(MTK_RESETTING, &eth->state);
>  
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> index 18a50529ce7b..a8066b3ee3ed 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> @@ -77,12 +77,24 @@
>  #define	MTK_HW_LRO_REPLACE_DELTA	1000
>  #define	MTK_HW_LRO_SDL_REMAIN_ROOM	1522
>  
> +/* Frame Engine Global Configuration */
> +#define MTK_FE_GLO_CFG		0x00
> +#define MTK_FE_LINK_DOWN_P3	BIT(11)
> +#define MTK_FE_LINK_DOWN_P4	BIT(12)
> +
>  /* Frame Engine Global Reset Register */
>  #define MTK_RST_GL		0x04
>  #define RST_GL_PSE		BIT(0)
>  
>  /* Frame Engine Interrupt Status Register */
>  #define MTK_INT_STATUS2		0x08
> +#define MTK_FE_INT_ENABLE	0x0c
> +#define MTK_FE_INT_FQ_EMPTY	BIT(8)
> +#define MTK_FE_INT_TSO_FAIL	BIT(12)
> +#define MTK_FE_INT_TSO_ILLEGAL	BIT(13)
> +#define MTK_FE_INT_TSO_ALIGN	BIT(14)
> +#define MTK_FE_INT_RFIFO_OV	BIT(18)
> +#define MTK_FE_INT_RFIFO_UF	BIT(19)
>  #define MTK_GDM1_AF		BIT(28)
>  #define MTK_GDM2_AF		BIT(29)
>  
> diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c
> index 269208a841c7..451a87b1bc20 100644
> --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
> +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
> @@ -730,6 +730,33 @@ int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)
>  	return __mtk_foe_entry_idle_time(ppe, entry->data.ib1);
>  }
>  
> +int mtk_ppe_prepare_reset(struct mtk_ppe *ppe)
> +{
> +	if (!ppe)
> +		return -EINVAL;
> +
> +	/* disable KA */
> +	ppe_clear(ppe, MTK_PPE_TB_CFG, MTK_PPE_TB_CFG_KEEPALIVE);
> +	ppe_clear(ppe, MTK_PPE_BIND_LMT1, MTK_PPE_NTU_KEEPALIVE);
> +	ppe_w32(ppe, MTK_PPE_KEEPALIVE, 0);
> +	usleep_range(10000, 11000);
> +
> +	/* set KA timer to maximum */
> +	ppe_set(ppe, MTK_PPE_BIND_LMT1, MTK_PPE_NTU_KEEPALIVE);
> +	ppe_w32(ppe, MTK_PPE_KEEPALIVE, 0xffffffff);
> +
> +	/* set KA tick select */
> +	ppe_set(ppe, MTK_PPE_TB_CFG, MTK_PPE_TB_TICK_SEL);
> +	ppe_set(ppe, MTK_PPE_TB_CFG, MTK_PPE_TB_CFG_KEEPALIVE);
> +	usleep_range(10000, 11000);
> +
> +	/* disable scan mode */
> +	ppe_clear(ppe, MTK_PPE_TB_CFG, MTK_PPE_TB_CFG_SCAN_MODE);
> +	usleep_range(10000, 11000);
> +
> +	return mtk_ppe_wait_busy(ppe);
> +}
> +
>  struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
>  			     int version, int index)
>  {
> diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h
> index ea64fac1d425..16b02e1d4649 100644
> --- a/drivers/net/ethernet/mediatek/mtk_ppe.h
> +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
> @@ -309,6 +309,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
>  void mtk_ppe_deinit(struct mtk_eth *eth);
>  void mtk_ppe_start(struct mtk_ppe *ppe);
>  int mtk_ppe_stop(struct mtk_ppe *ppe);
> +int mtk_ppe_prepare_reset(struct mtk_ppe *ppe);
>  
>  void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash);
>  
> diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
> index 59596d823d8b..0fdb983b0a88 100644
> --- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
> +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
> @@ -58,6 +58,12 @@
>  #define MTK_PPE_TB_CFG_SCAN_MODE		GENMASK(17, 16)
>  #define MTK_PPE_TB_CFG_HASH_DEBUG		GENMASK(19, 18)
>  #define MTK_PPE_TB_CFG_INFO_SEL			BIT(20)
> +#define MTK_PPE_TB_TICK_SEL			BIT(24)
> +
> +#define MTK_PPE_BIND_LMT1			0x230
> +#define MTK_PPE_NTU_KEEPALIVE			GENMASK(23, 16)
> +
> +#define MTK_PPE_KEEPALIVE			0x234
>  
>  enum {
>  	MTK_PPE_SCAN_MODE_DISABLED,
> -- 
> 2.39.0
> 

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