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Message-ID: <Y8afyunHKYDNMbRI@lunn.ch>
Date: Tue, 17 Jan 2023 14:16:58 +0100
From: Andrew Lunn <andrew@...n.ch>
To: yanhong wang <yanhong.wang@...rfivetech.com>
Cc: "Frank.Sae" <Frank.Sae@...or-comm.com>,
Peter Geis <pgwipeout@...il.com>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
"David S . Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
xiaogang.fan@...or-comm.com, fei.zhang@...or-comm.com,
hua.sun@...or-comm.com, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH net-next v1 1/3] dt-bindings: net: Add Motorcomm yt8xxx
ethernet phy Driver bindings
> Hi Andrew, i'm an engineer from StarFive Technology Co.
>
> This configuration is mainly to adapt to VF2 with JH7110 SoC.
> This is a defect in the design of JH7110. Only the basic delay
> configuration of PHY can't meet the delay needs of JH7110,
> must with the configuration of tx-clk-x-inverted together can
> gmac work normally. Otherwise, gmac cannot work normally at
> different rates. JH7110 has been taped and cannot be modified
> in design, so it can only be corrected on software.
So you have a choice of one PHY, since i don't know of any other PHY
with this capability. I hope this is well documented, since PHYs tend
to be considered interchangeable, use whatever is currently the
cheapest. And i assume you will fix the MAC for the next version of
the silicon?
So all these clock invert properties are fine.
I will take another look at the delay property..
Andrew
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