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Message-Id: <20230117153535.1945554-18-aaptel@nvidia.com>
Date: Tue, 17 Jan 2023 17:35:27 +0200
From: Aurelien Aptel <aaptel@...dia.com>
To: linux-nvme@...ts.infradead.org, netdev@...r.kernel.org,
sagi@...mberg.me, hch@....de, kbusch@...nel.org, axboe@...com,
chaitanyak@...dia.com, davem@...emloft.net, kuba@...nel.org
Cc: Ben Ben-Ishay <benishay@...dia.com>,
Aurelien Aptel <aaptel@...dia.com>, aurelien.aptel@...il.com,
smalin@...dia.com, malin1024@...il.com, ogerlitz@...dia.com,
yorayz@...dia.com, borisp@...dia.com
Subject: [PATCH v9 17/25] net/mlx5: Add NVMEoTCP caps, HW bits, 128B CQE and enumerations
From: Ben Ben-Ishay <benishay@...dia.com>
Add the necessary infrastructure for NVMEoTCP offload:
- Create mlx5_cqe128 structure for NVMEoTCP offload.
The new structure consist from the regular mlx5_cqe64 +
NVMEoTCP data information for offloaded packets.
- Add nvmetcp field to mlx5_cqe64, this field define the type
of the data that the additional NVMEoTCP part represents.
- Add nvmeotcp_zero_copy_en + nvmeotcp_crc_en bit
to the TIR, for identify NVMEoTCP offload flow
and tag_buffer_id that will be used by the
connected nvmeotcp_queues.
- Add new capability to HCA_CAP that represents the
NVMEoTCP offload ability.
Signed-off-by: Ben Ben-Ishay <benishay@...dia.com>
Signed-off-by: Or Gerlitz <ogerlitz@...dia.com>
Signed-off-by: Aurelien Aptel <aaptel@...dia.com>
Reviewed-by: Tariq Toukan <tariqt@...dia.com>
---
drivers/net/ethernet/mellanox/mlx5/core/fw.c | 6 ++
include/linux/mlx5/device.h | 51 +++++++++++++-
include/linux/mlx5/mlx5_ifc.h | 74 ++++++++++++++++++--
include/linux/mlx5/qp.h | 1 +
4 files changed, 127 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
index f34e758a2f1f..bfe540a4d588 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
@@ -286,6 +286,12 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
return err;
}
+ if (MLX5_CAP_GEN(dev, nvmeotcp)) {
+ err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_NVMEOTCP);
+ if (err)
+ return err;
+ }
+
return 0;
}
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index b50b15dbf3c1..8b13b0326fc1 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -263,6 +263,7 @@ enum {
enum {
MLX5_MKEY_MASK_LEN = 1ull << 0,
MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
+ MLX5_MKEY_MASK_XLT_OCT_SIZE = 1ull << 2,
MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
MLX5_MKEY_MASK_PD = 1ull << 7,
MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
@@ -787,7 +788,11 @@ struct mlx5_err_cqe {
struct mlx5_cqe64 {
u8 tls_outer_l3_tunneled;
- u8 rsvd0;
+ u8 rsvd16bit:4;
+ u8 nvmeotcp_zc:1;
+ u8 nvmeotcp_ddgst:1;
+ u8 nvmeotcp_resync:1;
+ u8 rsvd23bit:1;
__be16 wqe_id;
union {
struct {
@@ -836,6 +841,19 @@ struct mlx5_cqe64 {
u8 op_own;
};
+struct mlx5e_cqe128 {
+ __be16 cclen;
+ __be16 hlen;
+ union {
+ __be32 resync_tcp_sn;
+ __be32 ccoff;
+ };
+ __be16 ccid;
+ __be16 rsvd8;
+ u8 rsvd12[52];
+ struct mlx5_cqe64 cqe64;
+};
+
struct mlx5_mini_cqe8 {
union {
__be32 rx_hash_result;
@@ -871,6 +889,28 @@ enum {
#define MLX5_MINI_CQE_ARRAY_SIZE 8
+static inline bool cqe_is_nvmeotcp_resync(struct mlx5_cqe64 *cqe)
+{
+ return cqe->nvmeotcp_resync;
+}
+
+static inline bool cqe_is_nvmeotcp_crcvalid(struct mlx5_cqe64 *cqe)
+{
+ return cqe->nvmeotcp_ddgst;
+}
+
+static inline bool cqe_is_nvmeotcp_zc(struct mlx5_cqe64 *cqe)
+{
+ return cqe->nvmeotcp_zc;
+}
+
+/* check if cqe is zc or crc or resync */
+static inline bool cqe_is_nvmeotcp(struct mlx5_cqe64 *cqe)
+{
+ return cqe_is_nvmeotcp_zc(cqe) || cqe_is_nvmeotcp_crcvalid(cqe) ||
+ cqe_is_nvmeotcp_resync(cqe);
+}
+
static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
{
return (cqe->op_own >> 2) & 0x3;
@@ -1204,6 +1244,7 @@ enum mlx5_cap_type {
MLX5_CAP_VDPA_EMULATION = 0x13,
MLX5_CAP_DEV_EVENT = 0x14,
MLX5_CAP_IPSEC,
+ MLX5_CAP_DEV_NVMEOTCP = 0x19,
MLX5_CAP_DEV_SHAMPO = 0x1d,
MLX5_CAP_MACSEC = 0x1f,
MLX5_CAP_GENERAL_2 = 0x20,
@@ -1466,6 +1507,14 @@ enum mlx5_qcam_feature_groups {
#define MLX5_CAP_MACSEC(mdev, cap)\
MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
+#define MLX5_CAP_DEV_NVMEOTCP(mdev, cap)\
+ MLX5_GET(nvmeotcp_cap, \
+ (mdev)->caps.hca[MLX5_CAP_DEV_NVMEOTCP]->cur, cap)
+
+#define MLX5_CAP64_DEV_NVMEOTCP(mdev, cap)\
+ MLX5_GET64(nvmeotcp_cap, \
+ (mdev)->caps.hca[MLX5_CAP_DEV_NVMEOTCP]->cur, cap)
+
enum {
MLX5_CMD_STAT_OK = 0x0,
MLX5_CMD_STAT_INT_ERR = 0x1,
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 72f0020fc448..403496e1485d 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1449,7 +1449,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 event_cap[0x1];
u8 reserved_at_91[0x2];
u8 isolate_vl_tc_new[0x1];
- u8 reserved_at_94[0x4];
+ u8 reserved_at_94[0x2];
+ u8 nvmeotcp[0x1];
+ u8 reserved_at_97[0x1];
u8 prio_tag_required[0x1];
u8 reserved_at_99[0x2];
u8 log_max_qp[0x5];
@@ -3347,7 +3349,20 @@ struct mlx5_ifc_shampo_cap_bits {
u8 reserved_at_20[0x3];
u8 shampo_max_log_headers_entry_size[0x5];
u8 reserved_at_28[0x18];
+ u8 reserved_at_40[0x7c0];
+};
+
+struct mlx5_ifc_nvmeotcp_cap_bits {
+ u8 zerocopy[0x1];
+ u8 crc_rx[0x1];
+ u8 crc_tx[0x1];
+ u8 reserved_at_3[0x15];
+ u8 version[0x8];
+ u8 reserved_at_20[0x13];
+ u8 log_max_nvmeotcp_tag_buffer_table[0x5];
+ u8 reserved_at_38[0x3];
+ u8 log_max_nvmeotcp_tag_buffer_size[0x5];
u8 reserved_at_40[0x7c0];
};
@@ -3371,6 +3386,7 @@ union mlx5_ifc_hca_cap_union_bits {
struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
struct mlx5_ifc_shampo_cap_bits shampo_cap;
struct mlx5_ifc_macsec_cap_bits macsec_cap;
+ struct mlx5_ifc_nvmeotcp_cap_bits nvmeotcp_cap;
u8 reserved_at_0[0x8000];
};
@@ -3617,7 +3633,9 @@ struct mlx5_ifc_tirc_bits {
u8 disp_type[0x4];
u8 tls_en[0x1];
- u8 reserved_at_25[0x1b];
+ u8 nvmeotcp_zero_copy_en[0x1];
+ u8 nvmeotcp_crc_en[0x1];
+ u8 reserved_at_27[0x19];
u8 reserved_at_40[0x40];
@@ -3648,7 +3666,8 @@ struct mlx5_ifc_tirc_bits {
struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
- u8 reserved_at_2c0[0x4c0];
+ u8 nvmeotcp_tag_buffer_table_id[0x20];
+ u8 reserved_at_2e0[0x4a0];
};
enum {
@@ -11691,6 +11710,7 @@ enum {
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
+ MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_NVMEOTCP_TAG_BUFFER_TABLE = BIT_ULL(0x21),
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
};
@@ -11698,6 +11718,7 @@ enum {
MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
+ MLX5_GENERAL_OBJECT_TYPES_NVMEOTCP_TAG_BUFFER_TABLE = 0x21,
MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
};
@@ -11988,6 +12009,20 @@ struct mlx5_ifc_query_sampler_obj_out_bits {
struct mlx5_ifc_sampler_obj_bits sampler_object;
};
+struct mlx5_ifc_nvmeotcp_tag_buf_table_obj_bits {
+ u8 modify_field_select[0x40];
+
+ u8 reserved_at_40[0x20];
+
+ u8 reserved_at_60[0x1b];
+ u8 log_tag_buffer_table_size[0x5];
+};
+
+struct mlx5_ifc_create_nvmeotcp_tag_buf_table_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
+ struct mlx5_ifc_nvmeotcp_tag_buf_table_obj_bits nvmeotcp_tag_buf_table_obj;
+};
+
enum {
MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
@@ -12001,6 +12036,13 @@ enum {
enum {
MLX5_TRANSPORT_STATIC_PARAMS_ACC_TYPE_TLS = 0x1,
+ MLX5_TRANSPORT_STATIC_PARAMS_ACC_TYPE_NVMETCP = 0x2,
+ MLX5_TRANSPORT_STATIC_PARAMS_ACC_TYPE_NVMETCP_WITH_TLS = 0x3,
+};
+
+enum {
+ MLX5_TRANSPORT_STATIC_PARAMS_TI_INITIATOR = 0x0,
+ MLX5_TRANSPORT_STATIC_PARAMS_TI_TARGET = 0x1,
};
struct mlx5_ifc_transport_static_params_bits {
@@ -12023,7 +12065,20 @@ struct mlx5_ifc_transport_static_params_bits {
u8 reserved_at_100[0x8];
u8 dek_index[0x18];
- u8 reserved_at_120[0xe0];
+ u8 reserved_at_120[0x14];
+
+ u8 cccid_ttag[0x1];
+ u8 ti[0x1];
+ u8 zero_copy_en[0x1];
+ u8 ddgst_offload_en[0x1];
+ u8 hdgst_offload_en[0x1];
+ u8 ddgst_en[0x1];
+ u8 hddgst_en[0x1];
+ u8 pda[0x5];
+
+ u8 nvme_resync_tcp_sn[0x20];
+
+ u8 reserved_at_160[0xa0];
};
struct mlx5_ifc_tls_progress_params_bits {
@@ -12262,4 +12317,15 @@ struct mlx5_ifc_modify_page_track_obj_in_bits {
struct mlx5_ifc_page_track_bits obj_context;
};
+struct mlx5_ifc_nvmeotcp_progress_params_bits {
+ u8 next_pdu_tcp_sn[0x20];
+
+ u8 hw_resync_tcp_sn[0x20];
+
+ u8 pdu_tracker_state[0x2];
+ u8 offloading_state[0x2];
+ u8 reserved_at_44[0xc];
+ u8 cccid_ttag[0x10];
+};
+
#endif /* MLX5_IFC_H */
diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h
index 4657d5c54abe..bda53b241d71 100644
--- a/include/linux/mlx5/qp.h
+++ b/include/linux/mlx5/qp.h
@@ -227,6 +227,7 @@ struct mlx5_wqe_ctrl_seg {
#define MLX5_WQE_CTRL_OPCODE_MASK 0xff
#define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
+#define MLX5_WQE_CTRL_TIR_TIS_INDEX_SHIFT 8
enum {
MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
--
2.31.1
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