netdev - [PATCH v2 03/19] ARM: imx6q: skip ethernet refclock reconfiguration if enet_clk

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Date:   Tue, 17 Jan 2023 07:14:37 +0100
From:   Oleksij Rempel <o.rempel@...gutronix.de>
To:     Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Abel Vesa <abelvesa@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Richard Cochran <richardcochran@...il.com>
Cc:     Oleksij Rempel <o.rempel@...gutronix.de>, kernel@...gutronix.de,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        Russell King <linux@...linux.org.uk>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, netdev@...r.kernel.org
Subject: [PATCH v2 03/19] ARM: imx6q: skip ethernet refclock reconfiguration if enet_clk_ref is present

Current mach-imx6q code has following logic:
- if ptp clock of the ethernet controller node is attached to the SoC
  internal enet_ref clock, then we configure RMII reference clock pin as
  output by setting IOMUXC_GPR1 BIT(21).
  In this case - MAC (SoC) is the clock provider, PHY is the clock consumer.
- if ptp clock of the ethernet controller node is not attached to the
  enet_ref clock, then we configure RMII reference clock pin as input by
  clearing IOMUXC_GPR1 BIT(21).
  In this case - PHY is the clock provider, MAC is the clock consumer.

According to the Freescale MX6SDL ReferenceManual v4, IOMUXC_GPR1 BIT(21)
(page 2033) this configuration bit is not related to the PTP (IEEE1588)
clock:
21 ENET_CLK_SEL - choose enet reference clk mode:
   0 - get enet tx reference clk from pad (external OSC for both external
       PHY and Internal Controller)
   1 - get enet tx reference clk from internal clock from anatop (loopback
       through pad), this clock also sent out to external PHY.

According to the Documentation/devicetree/bindings/net/fsl,fec.yaml:
      The "ptp"(option), for IEEE1588 timer clock that requires the clock.
      The "enet_clk_ref"(option), for MAC transmit/receiver reference clock
      like RGMII TXC clock or RMII reference clock. It depends on board
      design, the clock is required if RGMII TXC and RMII reference clock
      source from SOC internal PLL.
      The "enet_out"(option), output clock for external device, like supply
      clock for PHY. The clock is required if PHY clock source from SOC.

We can see, that "enet_clk_ref" clock is the best fit for this purpose.
Other properties like "ptp" is designed for IEEE1588 and "enet_out" do
not have real functionality within imx related clock infrastructure.

Since the "enet_clk_ref" is not used by the imx6qdl devicetrees, we can
use it as indicator of potentially properly configured DT. At same time
we can keep ptp clock based logic as the fallback for old DTs.

Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
---
 arch/arm/mach-imx/mach-imx6q.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index c9d7c29d95e1..7f6200925752 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -79,7 +79,7 @@ static void __init imx6q_enet_phy_init(void)
 static void __init imx6q_1588_init(void)
 {
 	struct device_node *np;
-	struct clk *ptp_clk;
+	struct clk *ptp_clk, *fec_enet_ref;
 	struct clk *enet_ref;
 	struct regmap *gpr;
 	u32 clksel;
@@ -90,6 +90,14 @@ static void __init imx6q_1588_init(void)
 		return;
 	}
 
+	/*
+	 * If enet_clk_ref configured, we assume DT did it properly and .
+	 * clk-imx6q.c will do needed configuration.
+	 */
+	fec_enet_ref = of_clk_get_by_name(np, "enet_clk_ref");
+	if (!IS_ERR(fec_enet_ref))
+		goto put_node;
+
 	ptp_clk = of_clk_get(np, 2);
 	if (IS_ERR(ptp_clk)) {
 		pr_warn("%s: failed to get ptp clock\n", __func__);
-- 
2.30.2