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Message-ID: <Y8qIoxpLj2uiRM1Q@shell.armlinux.org.uk>
Date: Fri, 20 Jan 2023 12:27:15 +0000
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Bjørn Mork <bjorn@...k.no>
Cc: netdev@...r.kernel.org, Felix Fietkau <nbd@....name>,
John Crispin <john@...ozen.org>,
Sean Wang <sean.wang@...iatek.com>,
Mark Lee <Mark-MC.Lee@...iatek.com>,
Lorenzo Bianconi <lorenzo@...nel.org>,
Daniel Golle <daniel@...rotopia.org>,
Alexander Couzens <lynxis@...0.eu>
Subject: Re: [PATCH v2 net 1/3] net: mediatek: sgmii: ensure the SGMII PHY is
powered down on configuration
On Fri, Jan 20, 2023 at 11:49:45AM +0100, Bjørn Mork wrote:
> From: Alexander Couzens <lynxis@...0.eu>
>
> The code expect the PHY to be in power down which is only true after reset.
> Allow changes of the SGMII parameters more than once.
>
> Only power down when reconfiguring to avoid bouncing the link when there's
> no reason to - based on code from Russell King.
>
> There are cases when the SGMII_PHYA_PWD register contains 0x9 which
> prevents SGMII from working. The SGMII still shows link but no traffic
> can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
> taken from a good working state of the SGMII interface.
>
> Suggested-by: Russell King (Oracle) <linux@...linux.org.uk>
> Signed-off-by: Alexander Couzens <lynxis@...0.eu>
> [ bmork: rebased and squashed into one patch ]
> Signed-off-by: Bjørn Mork <bjorn@...k.no>
Reviewed-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
Thanks!
--
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