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Message-ID: <Y85gevlt7u/0KpWp@corigine.com>
Date: Mon, 23 Jan 2023 11:24:58 +0100
From: Simon Horman <simon.horman@...igine.com>
To: Bjørn Mork <bjorn@...k.no>
Cc: netdev@...r.kernel.org, Felix Fietkau <nbd@....name>,
John Crispin <john@...ozen.org>,
Sean Wang <sean.wang@...iatek.com>,
Mark Lee <Mark-MC.Lee@...iatek.com>,
Lorenzo Bianconi <lorenzo@...nel.org>,
Russell King <linux@...linux.org.uk>,
Daniel Golle <daniel@...rotopia.org>,
Alexander Couzens <lynxis@...0.eu>,
Russell King <rmk+kernel@...linux.org.uk>
Subject: Re: [PATCH v3 net 1/3] net: mediatek: sgmii: ensure the SGMII PHY is
powered down on configuration
On Sun, Jan 22, 2023 at 10:21:51PM +0100, Bjørn Mork wrote:
> From: Alexander Couzens <lynxis@...0.eu>
>
> The code expect the PHY to be in power down which is only true after reset.
> Allow changes of the SGMII parameters more than once.
>
> Only power down when reconfiguring to avoid bouncing the link when there's
> no reason to - based on code from Russell King.
>
> There are cases when the SGMII_PHYA_PWD register contains 0x9 which
> prevents SGMII from working. The SGMII still shows link but no traffic
> can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
> taken from a good working state of the SGMII interface.
>
> Suggested-by: Russell King (Oracle) <linux@...linux.org.uk>
> Signed-off-by: Alexander Couzens <lynxis@...0.eu>
> [ bmork: rebased and squashed into one patch ]
> Reviewed-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
> Signed-off-by: Bjørn Mork <bjorn@...k.no>
> ---
> drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 ++
> drivers/net/ethernet/mediatek/mtk_sgmii.c | 39 +++++++++++++++------
> 2 files changed, 30 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> index dff0e3ad2de6..70e729468a95 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> @@ -1067,11 +1067,13 @@ struct mtk_soc_data {
> * SGMII modes
> * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
> * @pcs: Phylink PCS structure
> + * @interface: Currently configured interface mode
> */
> struct mtk_pcs {
> struct regmap *regmap;
> u32 ana_rgc3;
nit: on x86_64 (at least) there is a 4 byte hole here.
It could be filled by the interface field.
> struct phylink_pcs pcs;
> + phy_interface_t interface;
> };
...
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