netdev - Re: [PATCH] PCI: Add ACS quirk for Wangxun NICs

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Message-ID: <20230201153750.GA1864705@bhelgaas>
Date:   Wed, 1 Feb 2023 09:37:50 -0600
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Mengyuan Lou <mengyuanlou@...-swift.com>
Cc:     netdev@...r.kernel.org, linux-pci@...r.kernel.org
Subject: Re: [PATCH] PCI: Add ACS quirk for Wangxun NICs

On Wed, Feb 01, 2023 at 06:47:03PM +0800, Mengyuan Lou wrote:
> The Wangxun 1G/10G NICs may be multi-function devices. They do
> not advertise ACS capability.
> Add an ACS quirk for these devices so the functions can be in
> independent IOMMU groups.

Thanks for the patch!

The commit log and the code comment do not explicitly say that the
hardware implementation blocks transactions between functions.

Can you clarify this by verifying (a) you have direct knowledge that
the hardware *does* block those transactions, and (b) that the
following text is accurate:

  The Wangxun 1G/10G NICs may be multi-function devices. They do not
  advertise an ACS capability, but the hardware implementation always
  blocks peer-to-peer transactions between the functions.

  Add an ACS quirk for these devices so the functions can be in
  independent IOMMU groups.

> + * Wangxun 10G/1G nics have no ACS capability.
> + * But the implementation could block peer-to-peer transactions between them
> + * and provide ACS-like functionality.

Also, if the following comment is accurate, please incorporate it:

  Wangxun 10G/1G NICs have no ACS capability, but on multi-function
  devices, the hardware does block peer-to-peer transactions between
  the functions and provides ACS-like functionality.

"Implementation *could* block peer-to-peer transactions" doesn't say
whether it actually *does*.

If this all makes sense, please repost the patch with updated text.  I
don't want to update it myself because I don't know anything about the
NICs and I don't want to make assumptions.

Bjorn

> + */
> +static int  pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags)
> +{
> +	switch (dev->device) {
> +	case 0x0100 ... 0x010F:
> +	case 0x1001:
> +	case 0x2001:
> +		return pci_acs_ctrl_enabled(acs_flags,
> +			PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
> +	}
> +
> +	return false;
> +}
> +
>  static const struct pci_dev_acs_enabled {
>  	u16 vendor;
>  	u16 device;
> @@ -4980,6 +4998,8 @@ static const struct pci_dev_acs_enabled {
>  	{ PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
>  	/* Zhaoxin Root/Downstream Ports */
>  	{ PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
> +	/* Wangxun nics */
> +	{ PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
>  	{ 0 }
>  };
>  
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index b362d90eb9b0..bc8f484cdcf3 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -3012,6 +3012,8 @@
>  #define PCI_DEVICE_ID_INTEL_VMD_9A0B	0x9a0b
>  #define PCI_DEVICE_ID_INTEL_S21152BB	0xb152
>  
> +#define PCI_VENDOR_ID_WANGXUN		0x8088
> +
>  #define PCI_VENDOR_ID_SCALEMP		0x8686
>  #define PCI_DEVICE_ID_SCALEMP_VSMP_CTL	0x1010
>  
> -- 
> 2.39.1
>