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Message-ID: <Y90U7ydTIxox/Gey@lunn.ch>
Date: Fri, 3 Feb 2023 15:06:39 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Daniel Golle <daniel@...rotopia.org>
Cc: netdev@...r.kernel.org, linux-mediatek@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Russell King <linux@...linux.org.uk>,
Heiner Kallweit <hkallweit1@...il.com>,
Lorenzo Bianconi <lorenzo@...nel.org>,
Mark Lee <Mark-MC.Lee@...iatek.com>,
John Crispin <john@...ozen.org>, Felix Fietkau <nbd@....name>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Matthias Brugger <matthias.bgg@...il.com>,
DENG Qingfang <dqfext@...il.com>,
Landen Chao <Landen.Chao@...iatek.com>,
Sean Wang <sean.wang@...iatek.com>,
Paolo Abeni <pabeni@...hat.com>,
Jakub Kicinski <kuba@...nel.org>,
Eric Dumazet <edumazet@...gle.com>,
"David S. Miller" <davem@...emloft.net>,
Vladimir Oltean <olteanv@...il.com>,
Florian Fainelli <f.fainelli@...il.com>,
Jianhui Zhao <zhaojh329@...il.com>,
Bjørn Mork <bjorn@...k.no>
Subject: Re: [PATCH 2/9] net: ethernet: mtk_eth_soc: set MDIO bus clock
frequency
> static int mtk_mdio_init(struct mtk_eth *eth)
> {
> struct device_node *mii_np;
> + int clk = 25000000, max_clk = 2500000, divider = 1;
> int ret;
> + u32 val;
Reverse Christmas tree please.
> +
> + if (!of_property_read_u32(mii_np, "clock-frequency", &val))
> + max_clk = val;
> +
> + while (clk / divider > max_clk) {
> + if (divider >= 63)
> + break;
> +
> + divider++;
> + };
Please add some range checks here. Return -EINVAL if val > max_clock.
Also, if divider = 63 indicating the requested clock is too slow.
> +
> + val = mtk_r32(eth, MTK_PPSC);
> + val |= PPSC_MDC_TURBO;
> + mtk_w32(eth, val, MTK_PPSC);
> +
> + /* Configure MDC Divider */
> + val = mtk_r32(eth, MTK_PPSC);
> + val &= ~PPSC_MDC_CFG;
> + val |= FIELD_PREP(PPSC_MDC_CFG, divider);
> + mtk_w32(eth, val, MTK_PPSC);
Can these two writes to MTK_PPSC be combined into one?
val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
Andrew
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