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Message-ID: <20230203214844.jqvhcdyuvrjf5dxg@skbuf>
Date: Fri, 3 Feb 2023 23:48:44 +0200
From: Vladimir Oltean <olteanv@...il.com>
To: Daniel Golle <daniel@...rotopia.org>
Cc: netdev@...r.kernel.org, linux-mediatek@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Russell King <linux@...linux.org.uk>,
Heiner Kallweit <hkallweit1@...il.com>,
Lorenzo Bianconi <lorenzo@...nel.org>,
Mark Lee <Mark-MC.Lee@...iatek.com>,
John Crispin <john@...ozen.org>, Felix Fietkau <nbd@....name>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Matthias Brugger <matthias.bgg@...il.com>,
DENG Qingfang <dqfext@...il.com>,
Landen Chao <Landen.Chao@...iatek.com>,
Sean Wang <sean.wang@...iatek.com>,
Paolo Abeni <pabeni@...hat.com>,
Jakub Kicinski <kuba@...nel.org>,
Eric Dumazet <edumazet@...gle.com>,
"David S. Miller" <davem@...emloft.net>,
Florian Fainelli <f.fainelli@...il.com>,
Andrew Lunn <andrew@...n.ch>,
Jianhui Zhao <zhaojh329@...il.com>,
Bjørn Mork <bjorn@...k.no>
Subject: Re: [PATCH 2/9] net: ethernet: mtk_eth_soc: set MDIO bus clock
frequency
On Fri, Feb 03, 2023 at 07:01:01AM +0000, Daniel Golle wrote:
> Set MDIO bus clock frequency and allow setting a custom maximum
> frequency from device tree.
>
> Signed-off-by: Daniel Golle <daniel@...rotopia.org>
> ---
> drivers/net/ethernet/mediatek/mtk_eth_soc.c | 25 +++++++++++++++++++++
> drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> index a44ffff48c7b..9050423821dc 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> @@ -790,7 +790,9 @@ static const struct phylink_mac_ops mtk_phylink_ops = {
> static int mtk_mdio_init(struct mtk_eth *eth)
> {
> struct device_node *mii_np;
> + int clk = 25000000, max_clk = 2500000, divider = 1;
Would be good if constant values (clk) weren't put in variables.
> int ret;
> + u32 val;
>
> mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
> if (!mii_np) {
> @@ -818,6 +820,29 @@ static int mtk_mdio_init(struct mtk_eth *eth)
> eth->mii_bus->parent = eth->dev;
>
> snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
> +
> + if (!of_property_read_u32(mii_np, "clock-frequency", &val))
> + max_clk = val;
Checking for valid range? There should also probably be a dt-bindings
patch for this.
> +
> + while (clk / divider > max_clk) {
> + if (divider >= 63)
> + break;
> +
> + divider++;
> + };
uhm, "divider = min(DIV_ROUND_UP(25000000, max_clk), 63);"? I don't
think the compiler is smart enough to optimize away this loop.
> +
> + val = mtk_r32(eth, MTK_PPSC);
> + val |= PPSC_MDC_TURBO;
> + mtk_w32(eth, val, MTK_PPSC);
What does "TURBO" do and why do you set it unconditionally?
> +
> + /* Configure MDC Divider */
> + val = mtk_r32(eth, MTK_PPSC);
> + val &= ~PPSC_MDC_CFG;
> + val |= FIELD_PREP(PPSC_MDC_CFG, divider);
> + mtk_w32(eth, val, MTK_PPSC);
> +
> + dev_dbg(eth->dev, "MDC is running on %d Hz\n", clk / divider);
> +
> ret = of_mdiobus_register(eth->mii_bus, mii_np);
>
> err_put_node:
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> index 7230dcb29315..724815ae18a0 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> @@ -363,6 +363,11 @@
> #define RX_DMA_VTAG_V2 BIT(0)
> #define RX_DMA_L4_VALID_V2 BIT(2)
>
> +/* PHY Polling and SMI Master Control registers */
> +#define MTK_PPSC 0x10000
> +#define PPSC_MDC_CFG GENMASK(29, 24)
> +#define PPSC_MDC_TURBO BIT(20)
> +
> /* PHY Indirect Access Control registers */
> #define MTK_PHY_IAC 0x10004
> #define PHY_IAC_ACCESS BIT(31)
> --
> 2.39.1
>
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