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Message-ID: <Y+e74UIV/Td91lKB@lunn.ch>
Date: Sat, 11 Feb 2023 17:01:37 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
Cc: Lee Jones <lee@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Emil Renner Berthing <kernel@...il.dk>,
Conor Dooley <conor@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Giuseppe Cavallaro <peppe.cavallaro@...com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu <joabreu@...opsys.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Richard Cochran <richardcochran@...il.com>,
Sagar Kadam <sagar.kadam@...ive.com>,
Yanhong Wang <yanhong.wang@...rfivetech.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
netdev@...r.kernel.org, linux-riscv@...ts.infradead.org,
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linux-arm-kernel@...ts.infradead.org, kernel@...labora.com
Subject: Re: [PATCH 07/12] dt-bindings: net: Add StarFive JH7100 SoC
> + starfive,gtxclk-dlychain:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: GTX clock delay chain setting
Please could you add more details to this. Is this controlling the
RGMII delays? 0ns or 2ns?
> + gmac: ethernet@...20000 {
> + compatible = "starfive,jh7100-dwmac", "snps,dwmac";
> + reg = <0x0 0x10020000 0x0 0x10000>;
> + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
> + <&clkgen JH7100_CLK_GMAC_AHB>,
> + <&clkgen JH7100_CLK_GMAC_PTP_REF>,
> + <&clkgen JH7100_CLK_GMAC_GTX>,
> + <&clkgen JH7100_CLK_GMAC_TX_INV>;
> + clock-names = "stmmaceth", "pclk", "ptp_ref", "gtxc", "tx";
> + resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
> + reset-names = "ahb";
> + interrupts = <6>, <7>;
> + interrupt-names = "macirq", "eth_wake_irq";
> + max-frame-size = <9000>;
> + phy-mode = "rgmii-txid";
This is unusual. Does your board have a really long RX clock line to
insert the 2ns delay needed on the RX side?
Andrew
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