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Message-ID: <Y+gVTOB09lz0M5b1@lunn.ch>
Date: Sat, 11 Feb 2023 23:23:08 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Vladimir Oltean <vladimir.oltean@....com>
Cc: Maxime Chevallier <maxime.chevallier@...tlin.com>,
davem@...emloft.net, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org, thomas.petazzoni@...tlin.com,
Jakub Kicinski <kuba@...nel.org>,
Eric Dumazet <edumazet@...gle.com>,
Paolo Abeni <pabeni@...hat.com>,
Florian Fainelli <f.fainelli@...il.com>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
linux-arm-kernel@...ts.infradead.org,
Ioana Ciornei <ioana.ciornei@....com>
Subject: Re: [PATCH net-next] net: pcs: tse: port to pcs-lynx
On Sat, Feb 11, 2023 at 11:52:29PM +0200, Vladimir Oltean wrote:
> On Fri, Feb 10, 2023 at 09:02:39PM +0100, Andrew Lunn wrote:
> > I was wondering if the glue could actually be made generic. The kernel
> > has a number of reasonably generic MMIO device drivers, which are just
> > given an address range and assume a logical mapping.
> >
> > Could this be made into a generic MDIO MMIO bus driver, which just
> > gets configured with a base address, and maybe a stride between
> > registers?
>
> This sounds interesting to me because I also have at least one other
> potential use for it. The "nxp,sja1110-base-tx-mdio" driver does basically
> just that, except it's SPI instead of MMIO. So if the generic driver was a
> platform device driver and it was aware of dev_get_regmap(), it could
> get reused.
>
> What I'm not sure of is the spacing between MDIO registers. For the
> SJA1110 CBTX PHY, the registers are 32-bit wide (but contain 16-bit
> values). So MII_BMCR is at offset 0x0, MII_BMSR at 0x4 etc. I'd imagine
> that other MDIO buses might have MII_BMSR at 0x2.
This is what i meant by stride. The distance between registers. As you
say, it could be 2 bytes, but also 4 bytes. It should be a
configuration parameter when instantiating such a generic driver.
Andrew
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