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Date: Sat, 11 Feb 2023 05:18:10 +0200 From: Cristian Ciocaltea <cristian.ciocaltea@...labora.com> To: Lee Jones <lee@...nel.org>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Emil Renner Berthing <kernel@...il.dk>, Conor Dooley <conor@...nel.org>, Palmer Dabbelt <palmer@...belt.com>, Paul Walmsley <paul.walmsley@...ive.com>, Albert Ou <aou@...s.berkeley.edu>, Giuseppe Cavallaro <peppe.cavallaro@...com>, Alexandre Torgue <alexandre.torgue@...s.st.com>, Jose Abreu <joabreu@...opsys.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>, Richard Cochran <richardcochran@...il.com>, Sagar Kadam <sagar.kadam@...ive.com>, Yanhong Wang <yanhong.wang@...rfivetech.com> Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, netdev@...r.kernel.org, linux-riscv@...ts.infradead.org, linux-stm32@...md-mailman.stormreply.com, linux-arm-kernel@...ts.infradead.org, kernel@...labora.com Subject: [PATCH 01/12] dt-bindings: riscv: sifive-ccache: Add compatible for StarFive JH7100 SoC Document the compatible for the SiFive Composable Cache Controller found on the StarFive JH7100 SoC. This also requires extending the 'reg' property to handle distinct ranges, as specified via 'reg-names'. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@...labora.com> --- .../bindings/riscv/sifive,ccache0.yaml | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index 31d20efaa6d3..2b864b2f12c9 100644 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -25,6 +25,7 @@ select: - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - starfive,jh7100-ccache required: - compatible @@ -37,6 +38,7 @@ properties: - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - starfive,jh7100-ccache - const: cache - items: - const: starfive,jh7110-ccache @@ -70,7 +72,13 @@ properties: - description: DirFail interrupt reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reg-names: + items: + - const: control + - const: sideband next-level-cache: true @@ -89,6 +97,7 @@ allOf: contains: enum: - sifive,fu740-c000-ccache + - starfive,jh7100-ccache - starfive,jh7110-ccache - microchip,mpfs-ccache @@ -106,12 +115,29 @@ allOf: Must contain entries for DirError, DataError and DataFail signals. maxItems: 3 + - if: + properties: + compatible: + contains: + const: starfive,jh7100-ccache + + then: + properties: + reg: + maxItems: 2 + + else: + properties: + reg: + maxItems: 1 + - if: properties: compatible: contains: enum: - sifive,fu740-c000-ccache + - starfive,jh7100-ccache - starfive,jh7110-ccache then: -- 2.39.1
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