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Message-Id: <20230211031821.976408-10-cristian.ciocaltea@collabora.com>
Date: Sat, 11 Feb 2023 05:18:18 +0200
From: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
To: Lee Jones <lee@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Emil Renner Berthing <kernel@...il.dk>,
Conor Dooley <conor@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Giuseppe Cavallaro <peppe.cavallaro@...com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu <joabreu@...opsys.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Richard Cochran <richardcochran@...il.com>,
Sagar Kadam <sagar.kadam@...ive.com>,
Yanhong Wang <yanhong.wang@...rfivetech.com>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
netdev@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, kernel@...labora.com
Subject: [PATCH 09/12] riscv: dts: starfive: Add dma-noncoherent for JH7100 SoC
The RISC-V architecture is by default coherent, as indicated by
CONFIG_OF_DMA_DEFAULT_COHERENT, but the StarFive JH7100 is not, hence
provide the dma-noncoherent property to the soc DT node.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
---
arch/riscv/boot/dts/starfive/jh7100.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 000447482aca..7109e70fdab8 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -114,6 +114,7 @@ soc {
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-noncoherent;
clint: clint@...0000 {
compatible = "starfive,jh7100-clint", "sifive,clint0";
--
2.39.1
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